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S3C84E5/C84E9/P84E9 A/D CONVERTER
15-3
Conversion Data Register High Byte (ADDATAH)
F8H, Set 1, Bank 0, Read only
LSBMSB .7 .6 .5 .4 .3 .2 .1 .0
Conversion Data Register Low Byte (ADDATAL)
F9H, Set 1, Bank 0, Read only
LSBMSB x x x x x x .1 .0
Figure 15-2. A/D Converter Data Register (ADDATAH, ADDATAL)
Input Pins
ADC0-ADC7
(P3.0-P3.7)
10-bit result is
loaded into
A/D Conversion
Data Register
To ADCON.3
(EOC Flag)
AVref
AVss
Analog
Comparator
ADCON.4-.6
(Select one input pin of the assigned)
ADCON.0
(ADC Enable)
ADCON.0
(A/D Conversion enable)
ADCON.2-.1
M
u
l
t
i
p
l
e
x
e
r
+
-
Clock
Selector
Successive
Approximation
Logic
10-bit D/A
Converter
Conversion Result
(ADDATAH,
ADDATAL)
To Data bus
fxx/16
fxx/8
fxx/4
fxx
Figure 15-3. A/D Converter Circuit Diagram