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INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9
5-4
Vectors SourcesLevels Reset(Clear)
Timer A match/capture
IRQ1
Timer A overflow
H/W, S/W
H/W, S/W
C0H
C2H
C4H
C6H
C8H
CAH
IRQ2
Timer 1(0) match/capture
Timer 1(0) overflow
Timer 1(1) match/capture
Timer 1(1) overflow
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
Timer B underflowBEHIRQ0
H/W
IRQ3
Watch timer S/WCCH
CEH
D0H
D2H
D4H
IRQ4
P2.0 external interrupt
P2.1 external interrupt
P2.2 external interrupt
P2.3 external interrupt
S/W
S/W
S/W
S/W
D6H
D8H
DAH
DCH
IRQ5
P2.4 external interrupt
P2.5 external interrupt
P2.6 external interrupt
P2.7 external interrupt
S/W
S/W
S/W
S/W
DEH
E0H
E2H
IRQ6
P4.0 external interrupt
P4.1 external interrupt
P4.2 external interrupt
S/W
S/W
S/W
E4H
E6H
IRQ7 UART data receive
UART data transmit
S/W
S/W
NOTES:
1. Within a given interrupt level, the lower vector address has high priority. For example, DCH has
higher priority than DEH within the level IRQ5 the priorities within each level are set at the factory.
2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control
register setting.
Figure 5-2. S3C84E5/C84E9/P84E9 Interrupt Structure