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S3C84E5/C84E9/P84E9 BASIC TIMER
10-3
BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any
value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H",
automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the
current CLKCON register setting), divided by 4096, as the BT clock.
The CPU is reset whenever a basic timer counter overflow occurs, During normal operation, the application program
must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must
be cleared (by writing a “1” to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will
not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal operation,
the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT
clear instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop
mode has been released by an external interrupt.
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts
increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When
BTCNT.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock
signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when stop mode is released:
1. During stop mode, a power-on reset or an interrupt occurs to trigger the Stop mode release and oscillation
starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an external interrupt
is used to release stop mode, the BTCNT value increases at the rate of the preset clock source.
3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows.
4. When a BTCNT.4 overflow occurs, normal CPU operation resumes.