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8-BIT TIMER A/B S3C84E5/C84E9/P84E9
11-2
FUNCTION DESCRIPTION
Timer A Interrupts (IRQ1, Vectors C0H and C2H)
The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/
capture interrupt (TAINT). TAOVF is interrupt level IRQ1, vector C2H. TAINT also belongs to interrupt level IRQ1, but
is assigned the separate vector address, C0H.
A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. A
timer A match/capture interrupt, TAINT pending condition is also cleared by hardware when it has been serviced.
Interval Timer Function
The timer A module can generate an interrupt: the timer A match interrupt (TAINT). TAINT belongs to interrupt level
IRQ1, and is assigned the separate vector address, C0H.
When the timer A match interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically
by hardware.
In interval timer mode, a match signal is generated and TAOUT is toggled when the counter value is identical to the
value written to the timer A reference data register, TADATA. The match signal generates a timer A match interrupt
(TAINT, vector C0H) and clears the counter.
If, for example, you write the value 10H to TADATA and 0AH to TACON, the counter will increment until it reaches
10H. At this point, the Timer A interrupt request is generated, the counter value is reset, and counting resumes.
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the TAOUT
pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to
the Timer A data register, TADATA. In PWM mode, however, the match signal does not clear the counter. Instead, it
runs continuously, overflowing at FFH, and then continues incrementing from 00H.
Although you can use the match signal to generate a timer A overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the TAOUT pin is held to Low level as long as the reference data value
is less than or equal to ( ≤ ) the counter value and then the pulse is held to High level for as long as the data value is
greater than ( > ) the counter value. One pulse width is equal to t
CLK
• 256.
Capture Mode
In capture mode, a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value
into the Timer A data register. You can select rising or falling edges to trigger this operation.
Timer A also gives you capture-input source: the signal edge at the TACAP pin. You select the capture input by
setting the value of the Timer A capture input selection bit in the port 0 control register, P0CONH, (set 1, bank 0,
E6H). When P0CONH.7-.6 is ‘00’ or ‘01’, the TACAP input or normal input is selected. When P0CONH.7-.6 is set to
1X, normal push-pull output is selected.
Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated whenever a
counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value is loaded into
the Timer A data register.
By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency, you
can calculate the pulse width (duration) of the signal that is being input at the TACAP pin.