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S3C84E5/C84E9/P84E9 CONTROL REGISTER
4-3
Table 4-3. Set 1, Bank 1 Registers
Register Name Mnemonic Decimal Hex R/W
Timer A, Timer 1 interrupt pending register TINTPND 224 E0H R/W
Timer A control register TACON 225 E1H R/W
Timer A data register TADATA 226 E2H R/W
Timer A counter register TACNT 227 E3H R
Timer 1(0) data register (High Byte) T1DATAH0 228 E4H R/W
Timer 1(0) data register (Low Byte) T1DATAL0 229 E5H R/W
Timer 1(1) data register (High Byte) T1DATAH1 230 E6H R/W
Timer 1(1) data register (Low Byte) T1DATAL1 231 E7H R/W
Timer 1(0) control register T1CON0 232 E8H R/W
Timer 1(1) control register T1CON1 233 E9H R/W
Timer 1(0) counter register (High Byte) T1CNTH0 234 EAH R
Timer 1(0) counter register (Low Byte) T1CNTL0 235 EBH R
Timer 1(1) counter register (High Byte) T1CNTH1 236 ECH R
Timer 1(1) counter register (Low Byte) T1CNTL1 237 EDH R
UART baud rate data register (High Byte) BRDATAH 238 EEH R/W
UART baud rate data register (Low Byte) BRDATAL 239 EFH R/W
Location F0H – FFH are not mapped