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S3C84E5/C84E9/P84E9 INSTRUCTION SET
6-85
TM — Test under Mask
TM dst,src
Operation: dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand (mask),
which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine
the result. The destination and the source operands are unaffected.
Flags: C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode
dst src
opc dst | src 2 4 72 r r
6 73 r lr
opc src dst 3 6 74 R R
6 75 R IR
opc dst src 3 6 76 R IM
Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TM R0,R1 → R0 = 0C7H, R1 = 02H, Z = "0"
TM R0,@R1 → R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
TM 00H,01H → Register 00H = 2BH, register 01H = 02H, Z = "0"
TM 00H,@01H → Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
TM 00H,#54H → Register 00H = 2BH, Z = "1"
In the first example, if the working register R0 contains the value 0C7H (11000111B) and the register
R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register
for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic
zero and can be tested to determine the result of the TM operation.