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S3C84E5/C84E9/P84E9 I/O PORTS
9-7
PORT 2
Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading
the port 2 data register, P2 at location E2H in set 1, bank 0. P2.0–P2.7 can serve as digital inputs, outputs (push
pull) or you can configure the following alternative functions:
— General-purpose digital I/O
— Alternative function: INT0– INT7
Port 2 Control Register (P2CONH, P2CONL)
Port 2 has two 8-bit control registers: P2CONH for P2.4–P2.7 and P2CONL for P2.0–P2.3. A reset clears the
P2CONH and P2CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to
select input or output mode (push-pull) and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using the
port 2 control registers must also be enabled in the associated peripheral module.
When you select output mode, a push-pull circuit is configured. In input mode, three different selections are
available:
— Schmitt trigger input and interrupt generation on falling signal edges.
— Schmitt trigger input and interrupt generation on rising signal edges.
— Schmitt trigger input with pull up resister and interrupt generation on falling signal edges.
Port 2 Interrupt Enable and Pending Registers (P2INT, P2INTPND)
To process external interrupts at the port 2 pins, two additional control registers are provided: the port 2 interrupt
enable register P2INT (ECH, set 1, bank 0) and the port 2 interrupt pending register P2INTPND (EDH, set 1, bank 0).
The port 2 interrupt pending register P2INTPND lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests by
polling the P2INTPND register at regular intervals.
When the interrupt enable bit of any port 4 pin is “1”, a rising or falling signal edge at that pin will generate an
interrupt request. The corresponding P2INTPND bit is then automatically set to “1” and the IRQ level goes low to
signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application
software must clear the pending condition by writing a “0” to the corresponding P2INTPND bit.