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INTERRUPT STRUCTURE S3C84E5/C84E9/P84E9
5-6
Table 5-1. Interrupt Vectors
Vector Address Interrupt Source Request Reset/Clear
Decimal
Value
Hex
Value
Interrupt
Level
Priority in
Level
H/W S/W
256 100H Basic timer (WDT) overflow nRESET – √
230 E6H UART transmit IRQ7 1 √
228 E4H UART receive 0 √
226 E2H P4.2 external interrupt IRQ6 2 √
224 E0H P4.1 external interrupt 1 √
222 DEH P4.0 external interrupt 0 √
220 DCH P2.7 external interrupt IRQ5 3 √
218 DAH P2.6external interrupt 2 √
216 D8H P2.5 external interrupt 1 √
214 D6H P2.4 external interrupt 0 √
212 D4H P2.3 external interrupt IRQ4 3 √
210 D2H P2.2 external interrupt 2 √
208 D0H P2.1external interrupt 1 √
206 CEH P2.0 external interrupt 0 √
204 CCH Watch timer IRQ3 – √
202 CAH Timer 1(1) overflow IRQ2 3 √ √
200 C8H Timer 1(1) match/capture 2 √ √
198 C6H Timer 1(0) overflow 1 √ √
196 C4H Timer 1(0) match/capture 0 √ √
194 C2H Timer A overflow IRQ1 1 √ √
192 C0H Timer A match/capture 0 √ √
190 BEH Timer B underflow IRQ0 – √
NOTES:
1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.