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S3C84E5/C84E9/P84E9 8-BIT TIMER A/B
11-3
TIMER A CONTROL REGISTER (TACON)
You use the timer A control register, TACON, to:
— Select the timer A operating mode (interval timer, capture mode and PWM mode)
— Select the timer A input clock frequency
— Clear the timer A counter, TACNT
— Enable the timer A overflow interrupt or timer A match/capture interrupt
— Clear timer A match/capture interrupt pending conditions
TACON is located in set 1, Bank 1 at address E1H, and is read/write addressable using Register addressing mode.
A reset clears TACON to '00H'. This sets timer A to normal interval timer mode, selects an input clock frequency of
fxx/1024, and disables all timer A interrupts. You can clear the timer A counter at any time during normal operation
by writing a "1" to TACON.3.
The timer A overflow interrupt (TAOVF) is interrupt level IRQ1 and has the vector address C2H. When a timer A
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.
To enable the timer A match/capture interrupt (IRQ1, vector C0H), you must write TACON.1 to "1". To generate the
exact time interval, you should write TACON.3 and .0 to “1”, which cleared counter and interrupt pending bit. When
interrupt service routine is served, the pending condition must be cleared by software by writing a ‘0’ to the interrupt
pending bit (TINTPND.0 or TINTPND.1).
.
Timer A Control Register (TACON)
00 = Interval mode (TAOUT mode)
E1H, Set 1, Bank 1, R/W, Reset: 00H
LSBMSB .7 .6 .5 .4 .3 .2 .1 .0
Timer A match/capture interrupt
enable bit:
0 = Disable interrupt
1 = Enable interrrupt
Timer A input clock selection bit:
00 = fxx/1024
01 = fxx/256
10 = fxx/64
11 = External clock (TACK)
Timer A operating mode selection bit:
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (OVF interrupt and match
interrupt can occur)
Timer A start/stop bit:
0 = Stop timer A
1 = Start timer A
Timer A overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrrupt
Timer A counter clear bit:
0 = No effect
1 = Clear the timer A counter (
when write)
NOTE:
When th counter clear bit(.3) is set, the 8-bit counter is cleared and
it also is cleared automatically.
Figure 11-1. Timer A Control Register (TACON)