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5.3PeripheralControlRegister(PCR)
SRIORegisters
Theperipheralcontrolregister(PCR)containsabitthatenablesordisablestheentireperipheralandone
bitforeverymodulewithintheperipheralwherethislevelofcontrolisdesired.Themodulecontrolbitscan
onlybewrittenwhentheperipheralitselfisenabled.Inaddition,thePCRhasemulationcontrolbitsfree
andsoft,whichcontroltheperipheralbehaviorduringemulationhalts.
Figure59.PeripheralControlRegister(PCR)
31-16
Reserved
R-0x00
LEGEND:R=Readonly;-n=valueafterreset
15-3210
ReservedPERESOFTFREE
N
R-0x00RW-RW-RW-
0x000x000x01
LEGEND:R=Readonly;-n=valueafterreset
Table30.PeripheralControlRegister(PCR)FieldDescriptions
BitFieldValueDescription
31-3ReservedReserved
2PERENPeripheralEnable.Controlstheflowofdatainthelogicallayeroftheperipheral.Asaninitiator,it
willpreventTXtransactiongenerationandasatarget,itwilldisableincomingrequests.Thisshould
bethelastenablebittotogglewhenbringingthedeviceoutofresettobeginnormaloperation.
0bDisablesdataflowcontrol
1bEnablesdataflowcontrol
1SOFTEmulationControl-SOFTbit
0FREEEmulationControl-FREEbit
SerialRapidIO(SRIO) 100SPRU976–March2006
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