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Source Address
DMA Read
Destination Address
Count
Byte Count
DSPAddress
RSV
Interrupt Req
001723
8
DestID
25 24
ID Size
27 26
xambs
29 28
Priority
OutPortID
31 30
Hop Count
Drbll
31 16 15
Packet
8 7 0
RapioIO Address/Config_offset
NodeID
CRC
16
Count*8
payload
2
xamsbs
1
wr ptr
29
address
32
ext addr
8
srcTID
4
wrsize
4
trans
8
sourceID
8
destID
4
ftype
2
tt
2
prio
3
rsv
5
ackID
TX Shared Buffer Pool
rdsize/
wsize
rdptr/
wptr
Count
translator
LSUn_REG4
LSUn_REG2
LSUn_REG3
LSUn_REG0
LSUn_REG1
LSUn_REG5
SRIOFunctionalDescription
Figure12.ExampleBurstNWRITE_R
ForWRITEcommands,thepayloadiscombinedwiththeheaderinformationfromthecontrol/command
registersandbufferedinthesharedTXbufferresourcepool.Finally,itisforwardedtotheTXFIFOfor
transmission.READcommandshavenopayload.Inthiscase,onlythecontrol/commandregisterfields
arebufferedandusedtocreateaRapidIONREADpacket,whichisforwardedtotheTXFIFO.
CorrespondingresponsepacketpayloadsfromREADtransactionsarebufferedinthesharedRXbuffer
resourcepoolwhenforwardedfromthereceiveports.Bothpostedandnon-postedoperationsrelyonthe
OutPortIDcommandregisterfieldtospecifytheappropriateoutputport/FIFO.
ThedataisburstinternallytotheLoad/StoremoduleattheDMAclockrate.
2.3.3.1DetailedDataPathDescription
TheLoad/StoremoduleisforgeneratingalloutgoingRapidIODirectI/Opackets.Anyreadorwrite
transaction,otherthanthemessagingprotocol,usesthisinterface.Inaddition,outgoingDOORBELL
packetsaregeneratedthroughthisinterface.
ThedatapathforthismoduleusesDMAbusastheDMAinterface.Theconfigurationbusisusedbythe
CPUtoaccessthecontrol/commandregisters.Theregisterscontaintransferdescriptorsthatareneeded
toinitiateREADandWRITEpacketgeneration.Afterthetransferdescriptorsarewritten,flowcontrol
statusisqueried.TheunitexaminestheDESTIDandPRIORITYfieldsofLSUn_REG4todetermineifthat
flowhasbeenXoffd.Additionally,thefreebufferstatusoftheTXFIFOischecked(basedonthe
OutPortIDregisterfield).Onlyaftertheflowcontrolaccessisgranted,andaTXFIFObufferhasbeen
allocated,canaDMAbusreadcommandbeissuedforpayloaddatatobemovedintothesharedTX
bufferpool.DataismovedfromthesharedbufferpooltotheappropriateoutputTXFIFOinsimple
sequentialorderbasedoncompletionoftheDMAbustransaction.However,iffabriccongestionoccurs,
prioritycanaffecttheorderinwhichthedataleavestheTXFIFOs.
Hereareorderingmechanismexists,whichtransmitsthehighestprioritypacketsfirstifRETRY
acknowledges.OnceintheFIFO,thedataisguaranteedtobetransmittedthroughthepins.Alternatively,
ifanintendedflowhasbeenshutdown,theperipheralsignalstheCPUwithaninterrupttonotifythatthe
packetwasnotsentandsetsthecompletioncodeto010binthestatusregister.Theregistersmustbe
helduntiltheinterruptserviceroutineiscompletebeforetheBSYsignalisreleased(BSY=0in
LSUn_REG6)andtheCPUcanthenrewriteoroverwritethetransferdescriptorswithnewdata.Figure13
illustratesthedatapathandbufferingthatisrequiredtosupporttheLoad/StoreModule.
36SerialRapidIO(SRIO)SPRU976–March2006
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