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SRIOFunctionalDescription
2.3.2SERDESanditsConfigurations
SRIOoffersmanybenefitstocustomersbyallowingascalablenon-proprietaryinterface.Withtheuseof
TI’sSERDESmacros,theperipheralisveryadaptableandbandwidthscalable.Thesameperipheralcan
beusedforallthreefrequencynodesspecifiedinV1.2oftheRapidIOspecification(1.25,2.5,and3.125
Gbps).Thisallowsyoutodesigntoonlyoneprotocolthroughoutthesystemandselectivelychoosethe
bandwidth,thuseliminatingtheneedforuser’sproprietaryprotocolsinmanyinstances,andprovidinga
fasterdesignturnandproductionramp.Sincethisinterfaceisserial,theapplicationspaceisnotlimitedto
asingleboard.Itwillpropagateintobackplaneapplicationsaswell.Integrationofthesemacrosonan
ASICorDSPallowsyoutoreducethenumberofdiscretecomponentsontheboardandeliminatesthe
needforbusdriverchips.
Additionally,therearesomevaluablefeaturesbuiltintoTISERDES.Systemoptimizationcanbeuniquely
managedtomeetindividualcustomerapplications.Forexample,controlregisterswithintheSERDES
allowyoutoadjusttheTXdifferentialoutputvoltage(Vod)onaperdriverbasis.Thisallowspower
savingsonshorttracelinks(onthesameboard)byreducingtheTXswing.Similarly,dataedgeratescan
beadjustedthroughthecontrolregisterstohelpreduceanyEMIaffects.Unusedlinkscanbeindividually
powereddownwithoutaffectingtheworkinglinks.
Becausethehigh-speedanalognatureoftheSERDESisoftenthemostcriticalportionoftheRapidIO
peripheral,goodtestaccessisimportant.
TheSERDESisaself-containedmacrowhichincludestransmitter(TX),receiver(RX),phase-locked-loop
(PLL),clockrecovery,serial-to-parallel(S2P),andparallel-to-serial(P2S)blocks.TheinternalPLL
multipliesauser-suppliedreferenceclock.AllloopfiltercomponentsofthePLLareonchip.Likewise,the
differentialTXandRXbufferscontainon-chipterminationresistors.Theonlyoff-chipcomponent
requirementisforDCblockingcapacitors.Thesecapacitorsareneededonlytoensureinteroperability
betweenvendorsandcanberemovedincaseswhereTIdevicestalktootherTIdevicesatthesame
voltagenode.TheSERDESaredesignedfor1.2V±5%operation.Thisprovidesforexcellentpower
efficiency.
2.3.2.1EnablingthePLL
ThePhysicallayerSERDEShasabuilt-inPLL,whichisusedfortheclockrecoverycircuitry.ThePLLis
responsibleforclockmultiplicationofaslowspeedreferenceclock.Thisreferenceclockhasnotiming
relationshiptotheserialdataandisasynchronoustoanyCPUsystemclock.Themultipliedhigh-speed
clockisonlyroutedwithintheSERDESblock,itisnotdistributedtotheremainingblocksoftheperipheral,
norisitaboundarysignaltothecoreofthedevice.Itisextremelyimportanttohaveagoodquality
referenceclock,andtoisolateitandthePLLfromallnoisesources.AuniqueReferenceClock
Distribution(RCD)macroisusedforthispurpose.SinceRapidIOrequires8b/10bencodeddata,the8-bit
modeoftheSERDESPLLwillnotbeused.
SERDES_CFGn_CNTL,SERDES_CFGRXn_CNTL,andSERDES_CFGTXn_CNTLregistersareusedto
configureSERDES.ToenabletheinternalPLL,theENPLLbitofSERDES_CFGn_CNTLmustbeset
high.Aftersettingthisbit,itisnecessarytoallow1µsfortheregulatortostabilize.Thereafter,thePLLwill
takenolongerthan200referenceclockcyclestolocktotherequiredfrequency,providedRIOCLKand
RIOCLKarestable.
Table4.BitsofSERDES_CFGn_CNTLRegister(0x120-0x12c)
BitNameValueDescription
31:10ReservedReserved.
9:8LBLoopbandwidth.Specifyloopbandwidthsettings.
00Frequencydependentbandwidth.ThePLLbandwidthissettoatwelfthofthefrequencyofRIOCLK
andRIOCLK.
01Reserved
10Lowbandwidth.ThePLLbandwidthissettoatwentiethofthefrequencyofRIOCLKandRIOCLK,
or3MHz(whicheverislarger).
11Highbandwidth.ThePLLbandwidthissettoaneighthofthefrequencyofRIOCLKandRIOCLK.
7:6ReservedReserved.
26SerialRapidIO(SRIO)SPRU976–March2006
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