Filter
Top Products
www.ti.com
5.13SERDESReceiveChannelConfigurationRegistersn(SERDES_CFGRXn_CNTL)
SRIORegisters
Therearefouroftheseregisters,tosupportfourports.
Figure69.SERDESReceiveChannelConfigurationRegistersn(SERDES_CFGRXn_CNTL)
312625242322191816
ReservedReservReservReservEQCDR
ededed
R-0R/W-0R/W-0R-0R/W-0R/W-0
15141312111087654210
LOSALIGNReservTERMINVPARATEBUSWIDTHReservENRX
edIRed
R/W-0R/W-0R-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND:R=Read,W=Write,n=valueatreset
Table40.SERDESReceiveChannelConfigurationRegistersn(SERDES_CFGRXn_CNTL)Field
Descriptions
BitFieldValueDescription
31:26ReservedReserved.
25ReservedReserved,keepaszeroduringwritestothisregister.
24ReservedReserved,keepaszeroduringwritestothisregister.
23ReservedReserved.
19:22EQEqualizer.Enablesandconfigurestheadaptiveequalizertocompensateforlossinthe
transmissionmedia.Forvalues,seeTable41.
18:16CDRClock/datarecovery.Configurestheclock/datarecoveryalgorithm.
000Firstorder.Phaseoffsettrackingupto±488ppm.
001Secondorder.Highestprecisionfrequencyoffsetmatchingbutpoorestresponsetochangesin
frequencyoffset,andlongestlocktime.Suitableforuseinsystemswithfixedfrequencyoffset.
010Secondorder.Mediumprecisionfrequencyoffsetmatching,frequencyoffsetchangeresponse
andlocktime.
011Secondorder.Bestresponsetochangesinfrequencyoffsetandfastestlocktime,butlowest
precisionfrequencyoffsetmatching.Suitableforuseinsystemswithspreadspectrumclocking.
100Firstorderwithfastlock.Phaseoffsettrackingupto±1953ppminthepresenceof..10101010..
trainingpattern,and±448ppmotherwise.
101Secondorderwithfastlock.Aspersetting001,butwithimprovedresponsetochangesin
frequencyoffsetwhennotclosetolock.
110Secondorderwithfastlock.Aspersetting010,butwithimprovedresponsetochangesin
frequencyoffsetwhennotclosetolock.
111Secondorderwithfastlock.Aspersetting011,butwithimprovedresponsetochangesin
frequencyoffsetwhennotclosetolock.
15:14LOSLossofsignal.Enableslossofsignaldetectionwith2selectablethresholds.
00Disabled.Lossofsignaldetectiondisabled.
01Highthreshold.Lossofsignaldetectionthresholdintherange85to195mV
dfpp
.Thissettingis
suitableforInfiniband.
10Lowthreshold.Lossofsignaldetectionthresholdintherange65-175mV
dfpp
.Thissettingis
suitableforPCI-EandS-ATA.
11Reserved
13:12ALIGNSymbolalignment.Enablesinternalorexternalsymbolalignment.
00Alignmentdisabled.Nosymbolalignmentwillbeperformedwhilethissettingisselected,orwhen
switchingtothisselectionfromanother.
01Commaalignmentenabled.Symbolalignmentwillbeperformedwheneveramisalignedcomma
symbolisreceived.
10Alignmentjog.Thesymbolalignmentwillbeadjustedbyonebitpositionwhenthismodeis
selected(i.e.,CFGRX[13:12]changesfrom0xto1x).
11Reserved
112SerialRapidIO(SRIO)SPRU976–March2006
SubmitDocumentationFeedback