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4.3InterruptConditionControlRegisters
InterruptConditions
TheDOORBELLpacket’s16-bitINFOfieldindicateswhichDOORBELLregisterinterruptbittoset.There
arefourDOORBELLregisters,eachcurrentlywith16bits,allowing64interruptsourcesorcircularbuffers.
EachbitcanbeassignedtoanycoreasdescribedbytheInterruptConditionRoutingRegisters.
Additionally,eachstatusbitisuser-definedfortheapplication.Forinstance,itmaybedesirabletosupport
multipleprioritieswithmultipleTIDcircularbufferspercoreifcontroldatausesahighpriority(i.e.,priority
=2),whiledatapacketsaresentonpriority0or1.Thisallowsthecontrolpacketstohavepreferencein
theswitchfabricandarriveasquicklyaspossible.SinceitmayberequiredtointerrupttheCPUforboth
dataandcontrolpacketprocessingseparately,separatecircularbuffersareused,andDOORBELL
packetsmustdistinguishbetweenthemforinterruptservicing.IfanyreservedbitintheDOORBELLinfo
fieldisset,anerrorresponseissent.
Theinterruptapproachtothemessagingprotocolissomewhatdifferent.Sincethesourcedeviceis
unawareofthedata'sphysicallocationinthedestinationdevice,andsinceeachmessagingpacket
containssizeandsegmentinformation,theperipheralcanautomaticallygeneratetheinterruptafterithas
successfullyreceivedallpacketsegmentscomprisingthecompletemessage.ThisDMAinterfaceuses
theCommunicationsPortProgrammingInterface(CPPI).Thisinterfaceisalink-listedapproachversusa
circularbufferapproach.DatabufferdescriptorswhichcontaininformationsuchasstartofPacket(SOP),
endofpacket(EOP),endofqueue(EOQ),andpacketlengtharebuiltfromtheRapidIOheaderfields.
Thedatabufferdescriptorsalsocontaintheaddressofthecorrespondingdatabufferasassignedbythe
receivedevice.Thedatabufferdescriptorsarethenlink-listedtogetherasmultiplepacketsarereceived.
Interruptsaregeneratedbytheperipheralafterallsegmentsofthemessagesarereceivedand
successfullytransferredthroughtheDMAbuswiththewrite-with-responsecommands.Interruptpacingis
alsoimplementedattheperipheralleveltomanagetheinterruptrate,asdescribedinSection4.6.
ErrorhandlingontheRapidIOlinkishandledbytheperipheral,andassuch,doesnotrequirethe
interventionofsoftwareforrecovery.ThisincludesCRCerrorsduetobitrateerrorsthatmaycause
erroneousorinvalidoperations.TheexceptiontothisstatementistheuseoftheRapidIOerror
managementextendedfeatures.Thisspecificationmonitorsandtabulatestheerrorsthatoccuronaper
portbasis.Ifthenumberoferrorsexceedsapre-determinedconfigurableamount,theperipheralshould
interrupttheCPUsoftwareandnotifythatanerrorconditionexits.Alternatively,ifasystemhostisused,
theperipheralmayissueaport-writeoperationtonotifythesystemsoftwareofabadlink.
Asystemreset,orCriticalErrorinterrupt,canbeinitializedthroughtheRapidIOlink.Thisprocedure
allowsanexternaldevicetoresetthelocaldevice,causingallstatemachineandconfigurationregistersto
resettotheiroriginalvalues.ThisisexecutedwiththeReset-DevicecommanddescribedinPartVI,
Section3.4.5oftheSerialspecification.FoursequentialReset-Devicecontrolsymbolsareneededto
avoidinadvertentresettingofadevice.
InterruptconditioncontrolregistersconfigurewhichCPUinterruptsaretobegeneratedandhow,based
ontheperipheralactivity.AllperipheralconditionsthatresultinaCPUinterruptaregroupedsothatthe
interruptcanbeaccessedintheminimumnumberofregisterreadspossible.
Foreachofthethreetypesofinterrupts(CPUservicing,errorstatus,andcriticalerror),therearetwosets
ofregisters:
•InterruptConditionStatusRegister(ICSR):Statusregisterthatreflectsthestateofeachconditionthat
cantriggertheinterrupt.
•InterruptConditionClearRegister(ICCR):Commandregisterthatallowseachconditiontobecleared.
Thisistypicallyrequiredpriortoenablingacondition,suchthatspuriousinterruptsarenotgenerated.
TheseregistersareaccessibleinthememorymapoftheCPU.TheCPUcontrolstheclearregister.The
statusregisterisreadablebytheCPUtodeterminetheperipheralcondition.
SPRU976–March2006SerialRapidIO(SRIO)75
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