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Configuration/Status
Register and Tables
(32-bit)
Output Buffers
(64-bit)
RapidIO Endpoint
IT Generator
ASIC
Device
RapidIO Endpoint
L2
CPU
Step 2. IT to CPU
for end transfer
completion
Step 1. ASIC
writes through
RapidIO to L2
SRIOFunctionalDescription
2.3.2.4SERDESConfigurationExample
rdata=SRIO_REGS->SERDES_CFG0_CNTL;
wdata=0x00000001;
mask=0x00000FFF;
mdata=(wdata&mask)|(rdata&~mask);
SRIO_REGS->SERDES_CFG0_CNTL=mdata;//3.125Gbps
SRIO_REGS->SERDES_CFG1_CNTL=mdata;//3.125Gbps
SRIO_REGS->SERDES_CFG2_CNTL=mdata;//3.125Gbps
SRIO_REGS->SERDES_CFG3_CNTL=mdata;//3.125Gbps
SRIO_REGS->SERDES_CFGRX0_CNTL=0x00081101;//enablerx,rate1
SRIO_REGS->SERDES_CFGRX1_CNTL=0x00081101;//enablerx,rate1
SRIO_REGS->SERDES_CFGRX2_CNTL=0x00081101;//enablerx,rate1
SRIO_REGS->SERDES_CFGRX3_CNTL=0x00081101;//enablerx,rate1
SRIO_REGS->SERDES_CFGTX0_CNTL=0x00010801;//enabletx,rate1
SRIO_REGS->SERDES_CFGTX1_CNTL=0x00010801;//enabletx,rate1
SRIO_REGS->SERDES_CFGTX2_CNTL=0x00010801;//enabletx,rate1
SRIO_REGS->SERDES_CFGTX3_CNTL=0x00010801;//enabletx,rate1
2.3.3DirectIO
TheDirectIO(Load/Store)moduleservesasthesourceofalloutgoingdirectI/Opackets.WithDirectI/O,
theRapidIOpacketcontainsthespecificaddresswherethedatashouldbestoredorreadinthe
destinationdevice.DirectI/OrequiresthataRapidIOsourcedevice,mustkeepalocaltableofaddresses
formemorywithinthedestinationdevice.IfaCRASICistalkingwithDSP,theASICwillhavedestination
circularbufferdescriptiontablesthatcontainDSPaddresses,buffersizes,andwritepointerinformation.
ThesetablesareinitializedbytheDSPuponsystembootaftertheinitialization/discoveryphase.Updates
tothetablecouldbemanagedcompletelybytheDSPthroughRapidIOmasterwrites.Oncethesetables
areestablished,theASICRapidIOcontrollerusesthisdatatocomputethedestinationaddressandinsert
itintothepacketheader.TheDSPRapidIOperipheralextractsthedestinationaddressfromthepacket
headerandtransfersthepayloadtoL2memoryviatheDMA.
WhenaCPUwantstosenddatafrommemorytoanexternalprocessingelement(PE)orreaddatafrom
anexternalPE,itmustprovidetheRIOperipheralvitalinformationaboutthetransfersuchasDSP
memoryaddress,targetdeviceID,targetdestinationaddress,packetpriority,etc.Essentially,ameans
mustexisttofillalltheheaderfieldsoftheRapidIOpacket.TheLoad/Storemoduleprovidesamechanism
tohandlethisinformationexchangeviaasetofMMRsactingastransferdescriptors.Theseregistersare
addressablebytheCPUthroughtheconfigurationbus.UponcompletionofawritetoLSU_Reg5,adata
transferisinitiatedforeitheranNREAD,NWRITE,NWRITE_R,SWRITE,ATOMIC,orMAINTENANCE
RapidIOtransaction.Somefields,suchastheRapidIOsrcTID/targetTIDfield,areassignedbyhardware
anddonothaveacorrespondingcommandregisterfield.
Figure9.Load/StoreDataTransferDiagram
32SerialRapidIO(SRIO)SPRU976–March2006
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