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CPPI block
CPU
DMA
Config bus access
L2 memory
Buffer
descriptor
dual-port
SRAM
(Nx20B)
Data buffer
Peripheral boundary
32
32
32
128
CPPI control
registers
SRIOFunctionalDescription
TeardownofanRxqueuecausesthefollowingactions:
•IfteardownisissuedbysoftwareduringthetimewhentheRXstatemachineisidle,thenthestate
machinewillimmediatelystarttheteardownprocedure:
–Ifthequeuetobetorndownisin-message(waitingforoneormoresegments),thenthequeuewill
betorndownandreportedwiththecurrentbufferdescriptor(teardownbitset,ownershipbit
cleared,CC=100b).Allotherfieldsofthebufferdescriptorareinvalid.Theperipheralcompletes
theteardownprocedurebyclearingtheHDPregister,settingtheCPregisterto0xFFFFFFFC,and
issuinganinterruptforthegivenqueue.Theteardowncommandregisterbitisautomatically
clearedbytheperipheral.
–Ifthequeueisnotin-message,andactive(nextdescriptoravailable),thenthenextdescriptorwill
befetchedandupdatedtoreportteardown(teardownbitset,ownershipbitcleared,CC=100b).All
otherfieldsofthebufferdescriptorareinvalid.Theperipheralcompletestheteardownprocedureby
clearingtheHDPregister,settingtheCPregisterto0xfffffffC,andissuinganinterruptforthegiven
queue.Theteardowncommandregisterbitisautomaticallyclearedbytheperipheral.
–Ifthequeueisnotin-message,butinactive(nextdescriptorunavailable),thennoadditionalbuffer
descriptorwillbewritten.TheHDPregisterandtheCPregisterremainunchanged.Aninterruptis
notissued.Theteardowncommandregisterbitisautomaticallyclearedbytheperipheral.
•IfteardownisissuedbysoftwareduringthetimewhentheRXUstatemachineisbusy,theteardown
procedurewillbepostponeduntilthestatemachineisidle.
AftertheteardownprocessiscompleteandtheinterruptisservicedbytheCPU,thesoftwaremust
re-initializetheRXqueuetorestartnormaloperation.
ThebufferdescriptorqueuesaremaintainedinlocalSRAMjustoutsideoftheperipheral.Thisallowsthe
quickestaccesstime,whilemaintainingalevelofconfigurabilityfordeviceimplementation.TheSRAMis
accessiblebytheCPUthroughtheconfigurationbus.Alternatively,thebufferdescriptorscoulduseL2
memoryaswell.
Figure21.CPPIBoundaryDiagram
48SerialRapidIO(SRIO)SPRU976–March2006
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