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1.25-3.125 Gbps
differential data
Rx
Clock
recovery
S2P
10b
Clk
8b/10b
decode
8b
Clock
recovery
Rx
8b8b/10b
decode
10b
ClkS2P
Clock
recovery
Rx
8b8b/10b
decode
10b
ClkS2P
Clock
recovery
Rx
8b8b/10b
decode
10b
ClkS2P
PLL
Tx
Tx
Tx
Tx
P2S
P2S
P2S
P2S
8b
8b
8b
8b
10b
8b/10b
coding
Clk
8b/10b
coding
8b/10b
coding
8b/10b
coding
10b
Clk
10b
Clk
10b
Clk
FIFO
FIFO
FIFO
FIFO
System
clock
Capability
registers
Control
Command
and status
registers
SERDES
Clock domain 2
Clock domain 3
Clock domain 1
DMA
bus
Packet Generation
Lane striping
Lane de-skew
CRC error detection
CRC generation
Buffering address and data handoff
FIFO
FIFO
FIFO
FIFO
SRIOFunctionalDescription
Figure4.SRIOPeripheralBlockDiagram
Withinthephysicallayer,thedatanextgoestothe8b/10bdecodeblock.8b/10bencodingisusedby
RapidIOtoensureadequatedatatransitionsfortheclockrecoverycircuits.Herethe20%encoding
overheadisremovedasthe10-bitdataisdecodedtotheraw8-bitdata.Atthispoint,therecoveredbyte
clockisstillbeingused.
Thenextstepisclocksynchronizationanddataalignment.ThesefunctionsarehandledbytheFIFOand
lanede-skewingblocks.TheFIFOprovidesanelasticstoremechanismusedtohandoffbetweenthe
recoveredclockdomainsandacommonsystemclock.AftertheFIFO,thefourlanesaresynchronizedin
frequencyandphase,whether1Xor4Xmodeisbeingused.TheFIFOis8wordsdeep.Thelane
de-skewisonlymeaningfulinthe4Xmode,whereitalignseachchannel’swordboundaries,suchthatthe
resulting32-bitwordiscorrectlyaligned.
TheCRCerrordetectionblockkeepsarunningtallyoftheincomingdataandcomputestheexpected
CRCvalueforthe1Xor4Xmode.TheexpectedvalueiscomparedagainsttheCRCvalueattheendof
thereceivedpacket.
Afterthepacketreachesthelogicallayer,thepacketfieldsaredecodedandthepayloadisbuffered.
Dependingonthetypeofreceivedpacket,thepacketroutingishandledbyfunctionalblockswhichcontrol
theDMAaccess.
2.1.2SRIOPackets
TheSRIOdatastreamconsistsofdatafieldspertainingtothelogicallayer,thetransportlayer,andthe
physicallayer.
•Thelogicallayerconsistsoftheheader(definingthetypeofaccess)andthepayload(ifpresent).
•Thetransportlayerispartiallydependentonthephysicaltopologyinthesystem,andconsistsof
sourceanddestinationIDsforthesendingandreceivingdevices.
•Thephysicallayerisdependentonthephysicalinterface(i.e.,serialversusparallelRapidIO)and
includespriority,acknowledgment,anderrorcheckingfields.
2.1.2.1OperationSequence
SRIOtransactionsarebasedonrequestandresponsepackets.Packetsarethecommunicationelement
betweenendpointdevicesinthesystem.Amasterorinitiatorgeneratesarequestpacketwhichis
transmittedtoatarget.Thetargetthengeneratesaresponsepacketbacktotheinitiatortocompletethe
transaction.
20SerialRapidIO(SRIO)SPRU976–March2006
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