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5.85PortControlCSRn(SPn_CTL)
SRIORegisters
Eachofthefourportsissupportedbyaregisterofthistype.
Figure141.PortControlCSRn(SPn_CTL)
31-3029-2726-24232221201918-16
PORT_WIDTHINITIALIZED_PORT_WIPORT_WIDTH_OVERRIPORTOUTPINPUTERROMULTIReserved
DTHDE_DISAUT_P_PORR_CHCAST
BLEORT_T_ENECK__PAR
ENABABLEDISABTICIP
LELEANT
R-0x01R-0x00RW-0x00RW-RW-RW-RW-RW-R-0x00
0x000x000x000x000x00
LEGEND:R=Readonly;-n=valueafterreset
15-43210
ReservedSTOPDROPPORTPORT
_POR_PAC_LOC_TYPE
T_FLDKET_EKOUT
_ENCNABL
_ENAE
BLE
R-0x00RW-RW-RW-R-
0x000x000x000x01
LEGEND:R=Readonly;-n=valueafterreset
Table115.PortControlCSRn(SPn_CTL)FieldDescriptions
BitFieldValueDescription
31-30PORT_WIDTHHardwarewidthoftheport(readonly).Only00bisvalidforSP1,SP2,andSP3
00bSingle-laneport
01bFour-laneport
10b-11bReserved
29-27INITIALIZED_POWidthoftheportsafterinitialized(readonly)
RT_WIDTH
000bSingle-laneport,lane0
001bSingle-laneport,lane2
010bFour-laneport
011b-Reserved
111b
26-24PORT_WIDTH_OSoftportconfigurationtooverridethehardwaresize
VERRIDE
000bNooverride
001bReserved
010bForcesinglelane,lane0
011bForcesinglelane,lane2
100b-Reserved
111b
23PORT_DISABLEPortdisable
0bPortreceivers/driversareenabled
1bPortreceivers/driversaredisabledandareunabletoreceive/transmittoanypacketsorcontrol
symbols
22OUTPUT_PORT_Outputportenable
ENABLE
0bPortisstoppedandnotenabledtoissueanypacketsexcepttorouteorrespondtoI/Ological
MAINTENANCEpackets,dependinguponthefunctionalityoftheprocessingelement.Control
symbolsarenotaffectedandaresentnormally.
1bPortisenabledtoissueanypackets
188SerialRapidIO(SRIO)SPRU976–March2006
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