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A0
A0
A2
A2
A1
A1
A3
A3
L2 offset 0x0
DSP defined MMR
offset 0x1000
Byte
lane 0
31
Byte
lane 3
DMA 32b
0
SRIOFunctionalDescription
2.3.8Endianness
RapidIOisbasedonbigendian.Thisisdiscussedindetailinsection2.4oftheRapidIOInterconnect
specification.Essentially,bigendianspecifiestheaddressorderingasthemostsignificantbit/bytefirst.
Forexample,inthe29-bitaddressfieldofaRapidIOpacket(showninFigure6)theleft-mostbitthatis
transmittedfirstintheserialbitstreamistheMSBoftheaddress.Likewise,thedatapayloadofthepacket
isdouble-wordalignedbig-endian,whichmeanstheMSBistransmittedfirst.Bit0ofallthe
RapidIO-definedMMRregistersistheMSB.
Allendianspecificconversionishandledwithintheperipheral.Fordouble-wordalignedpayloads,thedata
shouldbewrittencontiguouslyintomemorybeginningatthespecifiedaddress.Anyunalignedpayloads
willbepaddedandproperlyalignedwithinthe8-byteboundary.Inthiscase,WDPTR,RDSIZE,and
WRSIZERapidIOheaderfieldsindicatethebytepositionofthedatawithinthedouble-wordboundary.An
exampleofanunalignedtransferisshowninsection2.4oftheRapidIOInterconnectSpecification.
TherearenoendiantranslationrequirementsforaccessingthelocalMMRspace.Regardlessofthe
devicememoryendianconfiguration,allconfigurationbusaccessesareperformedon32-bitvaluesata
fixedaddressposition.Thebitpositionsinthe32-bitwordaredefinedbythisspecification.Thismeans
thatamemoryimagewhichwillbecopiedtoaMMRisidenticalbetweenlittleendianandbigendian
configurations.Configurationbusreadsareperformedinthesamemanner.Figure29illustratesthe
concept.ThedesiredoperationistolocallyupdateaserialRapidIOMMR(offset0x1000)withavalueof
0xA0A1A2A3,usingtheconfigurationbus.
Figure29.ConfigurationBusExample
WhenaccessingRapidIOdefinedMMRwithinanexternaldevice,RapidIOallows4B,8B,oranymultiple
ofadoublewordaccess(upto64B)forType8Maintenancepackets.Theperipheralonlysupports4B
accessesasthetarget,butcangenerateallsizesofrequestpackets.RapidIOisdefinedasbigendian
only,andhasdouble-wordalignedbigendianpacketpayloads.TheDMA,however,supportsbytewide
accesses.Theperipheralperformsendianconversiononthepayloadiflittleendianisusedonthedevice.
ThisconversionisnotonlyapplicableforType8packets,butisalsorelevantforalloutgoingpayloadsof
NWRITE,NWRITE_R,SWRITE,NREAD,andMessagepackets.Thismeansthatthememoryimageis
differentbetweenlittleendianandbigendianconfigurations,asshowninFigure30.
SPRU976–March2006SerialRapidIO(SRIO)63
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