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SRIOFunctionalDescription
Table9.EQBits
CFGRX[22:19]LowFreqGainZeroFreq(ate
28
(min))
0000Maximum-
0001AdaptiveAdaptive
001xReserved
01xxReserved
1000Adaptive1084MHz
1001805MHz
1010573MHz
1011402MHz
1100304MHz
1101216MHz
1110156MHz
1111135MHz
2.3.2.3EnablingtheTransmitter
Toenableatransmitterforserialization,theENTXbitoftheassociatedSERDES_CFGTXn_CNTL
registers(0x110–0x10c)mustbesethigh.WhenENTXislow,alldigitalcircuitrywithinthetransmitter
willbedisabled,andclockswillbegatedoff,withtheexceptionofthetransmitclock(TXBCLK[n])output,
whichwillcontinuetooperatenormally.Allcurrentsourceswithinthetransmitterwillbefullypowered
down,withtheexceptionoftheCMLdriver,whichwillremainpoweredupifboundaryscanisselected.
Table10.BitsofSERDES_CFGTXn_CNTLRegisters
BitFieldValueDescription
31:17ReservedReserved.
16ENFTPEnablefixedTXBCLKINnphase.EnablesfixedphaserelationshipofTXBCLKINnwithrespectto
TXBCLKn.
0Arbitraryphase.NorequiredphaserelationshipbetweenTXBCLKINnandTXBCLKn.
1Fixedphase.RequiresdirectconnectionofTXBCLKntoTXBCLKINnusingaminimumlength
netwithoutbuffers.
15:12DEDe-emphasis.Selectsoneof15outputde-emphasissettingsfrom4.76to71.42%.See
Table12.
11:9SWINGOutputswing.Selectsoneof8outputamplitudesettingsbetween125and1250mV
dfpp
.See
Table11.
8CMCommonmode.Adjuststhecommonmodetosuittheterminationattheattachedreceiver.
0Normalcommonmode.Commonmodenotadjusted.
1Raisedcommonmode.Commonmoderaisedby5%ofe
54
.
7INVPAIRInvertpolarity.InvertspolarityofTXPnandTXNn.
0Normalpolarity.TXPnconsideredtobepositivedataandTXNnnegative.
1Invertedpolarity.TXPnconsideredtobenegativedataandTXNnpositive.
6:5RATEOperatingrate.Selectsfull,halforquarterrateoperation.
00Fullrate.TwodatasamplestakenperPLLoutputclockcycle.
01Halfrate.OnedatasampletakenperPLLoutputclockcycle.
10Quarterrate.OnedatasampletakeneverytwoPLLoutputclockcycles.
11Reserved
30SerialRapidIO(SRIO)SPRU976–March2006
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