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SRIOFunctionalDescription
Table4.BitsofSERDES_CFGn_CNTLRegister(0x120-0x12c)(continued)
BitNameValueDescription
5:1MPYPLLmultiply.SelectPLLmultiplyfactorsbetween4and60.Multiplymodesshownbelow.
00004x
00015x
00106x
0011Reserved
01008x
010110x
011012x
011112.5x
100015x
100120x
101025x
1011Reserved
1100Reserved
110150x
111060x
1111Reserved
0ENPLLEnablePLL.EnablesthePLL.
BasedontheMPYvalue,thefollowinglinerateversusPLLoutputclockfrequencycanbeestimated:
Table5.LineRateversusPLLOutputClockFrequency
RateLineRatePLLOutputFrequencyRATESCALE
FullxGbps0.5xGHz0.5
HalfxGbpsxGHz1
QuarterxGbps2xGHz2
RIOCLKandRIOCLK
FREQ
=LINERATE×RATESCALE
MPY
TherateisdefinedbytheRATEbitsoftheSERDES_CFGRXn_CNTLregisterandthe
SERDES_CFGTXn_CNTLregister,respectively.
TheprimaryoperatingfrequencyoftheSERDESmacroisdeterminedbythereferenceclockfrequency
andPLLmultiplicationfactor.However,tosupportlowerfrequencyapplications,eachreceiverand
transmittercanalsobeconfiguredtooperateatahalforquarterofthisrateviatheRATEbitsofthe
SERDES_CFGRXn_CNTLandSERDES_CFGTXn_CNTLregistersasdescribedinTable6.
Table6.RATEBitEffects
ValueDescription
00Fullrate.TwodatasamplestakenperPLLoutputclockcycle.
01Halfrate.OnedatasampletakenperPLLoutputclockcycle.
10Quarterrate.OnedatasampletakeneverytwoPLLoutputclockcycles.
11Reserved.
SPRU976–March2006SerialRapidIO(SRIO)27
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