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InterruptConditions
•Bit21-TransactionwasnotsentduetoDMAdatatransfererror,LSU3
•Bit22-RetryDoorbellresponsereceivedorAtomicTest-and-swapwasnotallowed(semaphorein
use),LSU3
•Bit23-Packetnotsentduetounavailableoutboundcreditatgivenpriority,LSU3
•Bit24-Transactioncomplete,NoErrors(Posted/Non-posted),LSU4–seenote
•Bit25-Non-postedtransactionreceivedERRORresponse,orerrorinresponsepayload,LSU4
•Bit26-TransactionwasnotsentduetoXoffcondition,LSU4
•Bit27-TransactionwasnotsentduetounsupportedtransactiontypeorinvalidfieldencodingLSU4
•Bit28-TransactionTimeoutOccurred,LSU4
•Bit29-TransactionwasnotsentduetoDMAdatatransfererror,LSU4
•Bit30-RetryDoorbellresponsereceivedorAtomicTest-and-swapwasnotallowed(semaphorein
use),LSU4
•Bit31-Packetnotsentduetounavailableoutboundcreditatgivenpriority,LSU4
Note:EnableforthisinterruptisultimatelycontrolledbytheInterruptReqregisterbitofthe
Load/Storecommandregisters.Thisallowsenabling/disablingonaperrequestbasis.For
optimumLSUperformance,interruptpacingshouldnotbeusedontheLSUinterrupts.
Section4.6describesinterruptpacing.
Figure50.ERR_RST_EVNTError,Reset,andSpecialEventInterrupt
ERR_RST_EVNTInterruptConditionStatusRegisters(ICSR)(AddressOffset0x0270)
311716
ReservedICS16
R-0R/W-0
151211109873210
ReservedICS11ICS10ICS9ICS8ReservedICS2ICS1ICS0
R-0R/W-0R/W-0R/W-0R/W-0R-0R/W-0R/W-0R/W-0
LEGEND:R=Read,W=Write,n=valueatreset
ERR_RST_EVNTInterruptConditionClearRegisters(ICCR)(AddressOffset0x0278)
311716
ReservedICC16
R-0W-0
151211109873210
ReservedICC11ICC10ICC9ICC8ReservedICC2ICC1ICC0
R-0W-0W-0W-0W-0R-0W-0W-0W-0
LEGEND:R=Read,W=Write,n=valueatreset
Where:
•Bit0-Multi-casteventcontrolsymbolinterruptreceivedonanyport
•Bit1-Port-write-Inrequestreceivedonanyport
•Bit2-LogicalLayerErrorManagementEventCapture
•Bit8-Port0Error
•Bit9-Port1Error
•Bit10-Port2Error
•Bit11-Port3Error
•Bit16-DeviceResetInterruptfromanyport
80SerialRapidIO(SRIO)SPRU976–March2006
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