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1Overview
1.1GeneralRapidIOSystem
User'sGuide
SPRU976–March2006
SerialRapidIO(SRIO)
TheRapidIOperipheralusedintheTMS320C645xiscalledaserialRapidIO(SRIO).Thischapter
describesthegeneraloperationofaRapidIOsystem,howthismoduleisconnectedtotheoutsideworld,
thedefinitionsoftermsusedwithinthisdocument,andthefeaturessupportedandnotsupportedfor
SRIO.
RapidIO™isanon-proprietaryhigh-bandwidthsystemlevelinterconnect.Itisapacket-switched
interconnectintendedprimarilyasanintra-systeminterfaceforchip-to-chipandboard-to-board
communicationsatGigabyte-per-secondperformancelevels.Usesforthearchitecturecanbefoundin
connectedmicroprocessors,memory,andmemorymappedI/Odevicesthatoperateinnetworking
equipment,memorysubsystems,andgeneralpurposecomputing.PrinciplefeaturesofRapidIOinclude:
•Flexiblesystemarchitectureallowingpeer-to-peercommunication
•Robustcommunicationwitherrordetectionfeatures
•Frequencyandportwidthscalability
•Operationthatisnotsoftwareintensive
•Highbandwidthinterconnectwithlowoverhead
•Lowpincount
•Lowpower
•Lowlatency
1.1.1RapidIOArchitecturalHierarchy
RapidIOisdefinedasa3-layerarchitecturalhierarchy.
•Logicallayer:Specifiestheprotocols,includingpacketformats,whichareneededbyendpointsto
processtransactions
•Transportlayer:Definesaddressingschemestocorrectlyrouteinformationpacketswithinasystem
•Physicallayer:Containsthedevicelevelinterfaceinformationsuchastheelectricalcharacteristics,
errormanagementdata,andbasicflowcontroldata
IntheRapidIOarchitecture,asinglespecificationforthetransportlayeriscompatiblewithdiffering
specificationsforthelogicalandphysicallayers(seeFigure1).
14SerialRapidIO(SRIO)SPRU976–March2006
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