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LSU2
LSU4
LSU3
LSU1
MMR command
UDI interface
Load/store module
RapidIO transport
and physical layers
Port x transmission
FIFO queues
TX
FIFO
RX
FIFO
Peripheral boundary
Config bus
access
Write transfer
descriptors
CPU
I/O
pins
L2 memory
= Shared resource for CPPI and MAU
Shared
TX
data
Shared
RX
data
Response
timer
Control
and
arbitrator
DMA
request
DMA
response
SRIOFunctionalDescription
Figure13.Load/StoreModuleDataFlow
2.3.3.2TXOperation
WRITETransactions:
TheTXbuffersareimplementedinasingleSRAMandsharedbetweenmultiplecores.Astatemachine
arbitratesandassignsavailablebuffersbetweentheLSUs.WhentheDMAbusreadrequestis
transmitted,theappropriateTXbufferaddressisspecifiedwithinit.Thedatapayloadiswrittentothat
bufferthroughtheDMAbusresponsetransaction.Dependingonthearchitectureofthedevice,
interleavingofmulti-segmentedDMAbusresponsesfromtheDMAispossible.UponreceiptofaDMA
busreadresponsesegment,theunitchecksthecompletionstatusofthepayload.Notethatonlyone
payloadcanbecompletedinanysingleDMAbuscycle.TheLoad/Storemodulecanonlyforwardthe
packettotheTXFIFOafterthefinalpayloadbytefromtheDMAbusresponsehasbeenwrittenintothe
sharedmemorybuffer.OncethepacketisforwardedtotheTXFIFO,thesharedbuffercanbereleased
andmadeavailableforanewtransaction.
TheTXbufferspaceisdynamicallysharedamongalloutgoingsources,includingtheLoad/StoreUnit
(LSU)andtheTXCPPI,aswellastheresponsepacketsfromRXCPPIandtheMemoryAccessUnit
(MAU).Thus,thebufferspacememorymustbepartitionedtohandlepacketswithandwithoutpayloads.
A4.5KBbufferspaceisconfiguredtosupport16packetswithpayloadsupto256B,inadditionto16
packetswithoutpayloads.TheSRAMisconfiguredasa128-bitwidetwoport,whichmatchestheUDI
widthoftheTXFIFOs.
Dataleavesthesharedbufferpoolsequentiallyinorderofreceipt,notbasedonthepacketpriority.
However,iffabriccongestionoccurs,prioritycanaffecttheorderinwhichthedataleavestheTXFIFOs.A
reorderingmechanismexistshere,whichtransmitsthehighestprioritypacketsfirstifRETRY
acknowledges.
SPRU976–March2006SerialRapidIO(SRIO)37
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