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SRIOFunctionalDescription
Table13.Control/CommandRegisterFieldMapping(continued)
Control/CommandRegisterRapidIOPacketHeaderField
Field
PacketType4msb=4bftypefieldforallpacketsand
4lsb=4btransfieldforpackettypes2,5,8.
OutPortIDNotavailableinRapidIOheader.
Indicatestheoutputportnumberforthepackettobetransmittedfrom.SpecifiedbytheCPU
alongwithNodeID.
DrbllInfoRapidIOdoorbellinfofieldfortype10packets.
HopCountRapidIOhop_countfieldspecifiedforType8Maintenancepackets.
InterruptReqNotavailableinRapidIOheader.
CPUcontrolledrequestbitusedforinterruptgeneration.Typicallyusedinconjunctionwith
non-postedcommandstoalerttheCPUwhentherequesteddata/statusispresent.
0b-Aninterruptisnotrequesteduponcompletionofcommand
1b-Aninterruptisrequesteduponcompletionofcommand
Table14.StatusFields
StatusFieldFunction
BSYIndicatesstatusofthecommandregisters.
0b-Commandregistersareavailable(writable)fornextsetoftransferdescriptors
1b-Commandregistersarebusywithcurrenttransfer
CompletionCodeIndicatesthestatusofthependingcommand.
000b–Transactioncomplete,noerrors(Posted/Non-posted)
001b–TransactiontimeoutoccurredonNon-postedtransaction
010b–Transactioncomplete,packetnotsentduetoflowcontrolblockade(Xoff)
011b–Transactioncomplete,non-postedresponsepacket(type8and13)containedERRORstatus,or
responsepayloadlengthwasinerror
100b–Transactioncomplete,packetnotsentduetounsupportedtransactiontypeorinvalidprogramming
encodingforoneormoreLSUregisterfields
101b–DMAdatatransfererror
110b–RetryDOORBELLresponsereceived,orAtomicTest-and-swapwasnotallowed(semaphorein
use)
111b–Transactioncomplete,packetnotsentduetounavailableoutboundcreditatgivenpriority
(1)
(1)
StatusavailableonlywhenBsysignal=0.
FourLSUregistersetsexist.Thisallowsfouroutstandingrequestsforalltransactiontypesthatrequirea
response(i.e.,non-posted).Formulti-coredevices,softwaremanagestheusageoftheregisters.A
sharedconfigurationbusaccessesallregistersets.AsinglecoredevicecanutilizeallfourLSUblocks.
Figure11showsthetimingdiagramforaccessingtheLSUregisters.Bsysignalisdeasserted.LSU_Reg1
iswrittenonconfigurationbusclockcycleT0,LSU_Reg2iswrittenoncycleT1,LSU_Reg3iswrittenon
cycleT2,LSU_Reg4iswrittenoncycleT3.ThecommandregisterLSU_Reg5iswrittenoncycleT4.The
extendedaddressfieldinLSU_Reg0isassumedtobeconstantinthisexample.Uponcompletionofthe
writetothecommandregister(nextclockcycleT5),theBsysignalisasserted,atwhichpointthe
precedingcompletioncodeisinvalidandaccessestotheLSUregistersarenotallowed.Oncethe
transactioncompletes(eitherasasuccessfultransmission,orunsuccessfully,suchasflowcontrol
preventionorresponsetimeout)andanyrequiredinterruptserviceroutineiscompleted,theBsysignalis
deassertedandthecompletioncodebecomesvalidandtheregistersareaccessibleagain.
34SerialRapidIO(SRIO)SPRU976–March2006
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