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Overview
1.1.2RapidIOInterconnectArchitecture
Theinterconnectarchitectureisdefinedasapacketswitchedprotocolindependentofaphysicallayer
implementation.Figure2illustratestheinterconnectionsystem.
Figure2.RapidIOInterconnectArchitecture
(1)InfiniBand™isatrademarkoftheInfiniBandTradeAssociation.
1.1.31x/4xLP-Serial
Currently,therearetwophysicallayerspecificationsrecognizedbytheRapidIOTradeAssociation:8/16
LP-LVDSand1X/4XLP-Serial.The8/16LP-LVDSspecificationisapoint-to-pointsynchronousclock
sourcingDDRinterface.The1X/4XLP-Serialspecificationisapoint-to-point,ACcoupled,clockrecovery
interface.Thetwophysicallayerspecificationsarenotcompatible.
SRIOcomplieswiththe1X/4XLP-Serialspecification.Theserializer/deserializer(SERDES)technologyin
SRIOalsoalignswiththatspecification.
The1X/4XLP-Serialspecificationcurrentlycoversthreefrequencypoints:1.25,2.5,and3.125Gbps.This
definesthetotalbandwidthofeachdifferentialpairofI/Osignals.An8b/10bencodingschemeensures
ampledatatransitionsfortheclockrecoverycircuits.Duetothe8b/10bencodingoverhead,theeffective
databandwidthperdifferentialpairis1.0,2.0,and2.5Gbpsrespectively.SerialRapidIOonlyspecifies
theseratesforboththe1Xand4Xports.A1Xportisdefinedas1TXand1RXdifferentialpair.A4Xport
isacombinationoffourofthesepairs.Thisdocumentdescribesa4XRapidIOportthatcanalsobe
configuredasfour1Xports,thusprovidingascalableinterfacecapableofsupportingadatabandwidthof
1to10Gbps.
16SerialRapidIO(SRIO)SPRU976–March2006
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