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InterruptConditions
Figure47.RX_CPPIInterruptsUsingMessagingModeDataTransfers
RX_CPPIInterruptConditionStatusRegisters(ICSR)(AddressOffset0x0240)
3116
Reserved
R-0
1514131211109876543210
ICS15ICS14ICS13ICS12ICS11ICS10ICS9ICS8ICS7ICS6ICS5ICS4ICS3ICS2ICS1ICS0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND:R=Read,W=Write,n=valueatreset
RX_CPPIInterruptConditionClearRegisters(ICCR)(AddressOffset0x0248)
3116
Reserved
R-0
1514131211109876543210
ICC15ICC14ICC13ICC12ICC11ICC10ICC9ICC8ICC7ICC6ICC5ICC4ICC3ICC2ICC1ICC0
W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0
LEGEND:R=Read,W=Write,n=valueatreset
WhereICS0-RXCPPIinterrupt,bufferdescriptorqueue0,throughICS15-RXCPPIinterrupt,buffer
descriptorqueue15.
ClearingofanyICSRbitdependsontheCPUwritingthevalueoflastbufferdescriptorprocessedtothe
RXDMAStateCP.PorthardwareclearstheICSRbitonlyiftheCPvaluewrittenbytheCPUequalsthe
portwrittenvalueintheRXDMAStateCPregister.
Figure48.TX_CPPIInterruptsUsingMessagingModeDataTransfers
TX_CPPIInterruptConditionStatusRegisters(ICSR)(AddressOffset0x0250)
3116
Reserved
R-0
1514131211109876543210
ICS15ICS14ICS13ICS12ICS11ICS10ICS9ICS8ICS7ICS6ICS5ICS4ICS3ICS2ICS1ICS0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND:R=Read,W=Write,n=valueatreset
TX_CPPIInterruptConditionClearRegisters(ICCR)(AddressOffset0x0258)
3116
Reserved
R-0
1514131211109876543210
ICC15ICC14ICC13ICC12ICC11ICC10ICC9ICC8ICC7ICC6ICC5ICC4ICC3ICC2ICC1ICC0
W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0
LEGEND:R=Read,W=Write,n=valueatreset
SerialRapidIO(SRIO) 78SPRU976–March2006
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