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SRIOFunctionalDescription
Table25.EmulationControlSignals
NameBitAccessResetValueDescription
Free0R/W1bFREE=0,SOFTBittakeseffect
FREE=1,Freerunmode(defaultmode)-Peripheralignoresthe
EMUSUSPsignalandfunctionsnormally.
Soft1R/W0bSOFT=0->SoftStop(defaultmode)
SOFT=1->Hardstop–Allstatusregistersarefrozenindefaultstate.
(Modenotsupported)
PEREN2R/W0bPeripheralEnable.
0b–Disabled
1b–Enabled
Reserved31:30bReserved
FreeRunMode:(defaultmode)PeripheraldoesnotrespondtoEMUSUSPassertion.Modulefunctions
normally,irrespectiveofCPUemulationstate.
SoftStopMode:Peripheralgracefullyhaltsoperations.Theperipheralhaltsoperationatapointthat
makessensebothtotheinternalDMA/dataaccessoperationandtothepininterfaceasdescribedbelow,
afterfinishingpacketreceptionortransmissioninprogress:
•DMAbusDMAmaster:DMAbusrequestsinprogressareallowedtocomplete(DMAbushasno
meanstothrottlecommandinprogressfromtheMaster)DMAbusrequeststhatcorrespondtothe
samenetworkpacketareallowedtocomplete.NonewDMAbusrequestswillbegeneratedonthe
nextnewpacket.
•ConfigurationbusMMRinterface:AllMMRconfigurationbusrequestsareservicedasnormal.
•Events/interrupts:Newevents/interruptsarenotgeneratedtotheCPUfornewlyarrivingpackets.
Currenttransactionsareallowedtofinishandmaycauseaninterruptuponcompletion.
•Slavepininterface:Thepininterfacefunctionsasnormal.Ifbufferingisavailableintheperipheral,
theperipheralservicesexternallygeneratedrequestsaslongaspossible.Whentheinternalbuffers
areconsumed,theperipheralwillretryincomingnetworkpacketsinthephysicallayer.
•Masterpininterface:Nonewmasterrequestsaregenerated.Masterrequestsinprogressare
allowedtocomplete,includingallpacketslocatedinthephysicallayertransmitbuffers.
HardStopMode:Peripheralshouldhaltimmediately.ThismodeisnotsupportedintheRapidIO
peripheral.
2.3.11InitializationExample
2.3.11.1EnablingtheSRIOPeripherals
Whenthedeviceispoweredon,theSRIOperipheralisinadisabledstate.BeforeanySRIOspecific
initializationcantakeplace,theperipheralneedstobeenabled;otherwise,itsregisterscannotbewritten,
andthereadswillallreturnavalueofzero.
/*Glbenablesrio*/
SRIO_REGS->GBL_EN=0x00000001;
SRIO_REGS->BLK0_EN=0x00000001;//MMR_EN
SRIO_REGS->BLK5_EN=0x00000001;//PORT0_EN
SRIO_REGS->BLK1_EN=0x00000001;//LSU_EN
SRIO_REGS->BLK2_EN=0x00000001;//MAU_EN
SRIO_REGS->BLK3_EN=0x00000001;//TXU_EN
SRIO_REGS->BLK4_EN=0x00000001;//RXU_EN
SRIO_REGS->BLK6_EN=0x00000001;//PORT1_EN
SRIO_REGS->BLK7_EN=0x00000001;//PORT2_EN
SRIO_REGS->BLK8_EN=0x00000001;//PORT3_EN
SPRU976–March2006SerialRapidIO(SRIO)69
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