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5.14SERDESTransmitChannelConfigurationRegistersn(SERDES_CFGTXn_CNTL)
SRIORegisters
Therearefouroftheseregisters,tosupportfourports.
Figure70.SERDESTransmitChannelConfigurationRegistersn(SERDES_CFGTXn_CNTL)
311716
ReservedENFT
P
R-0R/W-0
151211987654210
DESWINGCMINVPARATEBUSWIDTHReservENTX
IRed
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND:R=Read,W=Write,n=valueatreset
Table42.SERDESTransmitChannelConfigurationRegistersn(SERDES_CFGTXn_CNTL)Field
Descriptions
BitFieldValueDescription
31:17ReserveReserved.
d
16ENFTPEnablefixedTXBCKLINnphase.EnablesfixedphaserelationshipofTXBCLKINnwithrespectto
TXBCLKn.
0Arbitraryphase.NorequiredphaserelationshipbetweenTXBCLKINnandTXBCLKn.
1Fixedphase.RequiresdirectconnectionofTXBCLKntoTXBCLKINnusingaminimumlengthnet
withoutbuffers.
15:12DEDe-emphasis.Selectsoneof15outputde-emphasissettingsfrom4.76to71.42%.SeeTable44.
11:9SWINGOutputswing.Selectsoneof8outputsamplitudesettingsbetween125and1250mV
dfpp
.See
Table43.
8CMCommonmode.Adjuststhecommonmodetosuittheterminationattheattachedreceiver.
0Normalcommonmode.Commonmodenotadjusted.
1Raisedcommonmode.Commonmoderaisedby5%ofe
54
.
7INVPAIRInvertpolarity.InvertspolarityofTXPnandTXNn.
0Normalpolarity.TXPnconsideredtobepositivedataandTXNnnegative.
1Invertedpolarity.TXPnconsideredtobenegativedataandTXNnpositive.
6:5RATEOperatingrate.Selectsfull,halforquarterrateoperation.
00Fullrate.TwodatasamplestakenperPLLoutputclockcycle.
01Halfrate.OnedatasampletakenperPLLoutputclockcycle.
10Quarterrate.OnedatasampletakeneverytwoPLLoutputclockcycles.
11Reserved
4:2BUS-Buswidth.Selectsthewidthoftheparallelinterface(10or8bit).
WIDTH
00010-bitoperation.DataisinputonTDn[9:0].TXBCLKnperiodis10bitperiods(4high,6low).
0018-bitoperation.DataisinputonTDn[9:2].TXBCLKnperiodis8bitperiods(4high,4low).TDn[1:0]
areignored.
01xReserved
1xxReserved
1ReserveReserved
d
0ENTXEnabletransmitter.Enablesthistransmitterwhenhigh.
SerialRapidIO(SRIO) 114SPRU976–March2006
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