Filter
Top Products
www.ti.com
SRIOFunctionalDescription
Table24.EnableandEnableStatusBitFieldDescriptions(continued)
NameBitAccessDescription
BLK8_EN_STAT0RIndicatesstateofBLK8_ENresetsignal.
0=Logicalblock8inresetandclockisoff
1=Logicalblock8enabledandclocking
TheGBL_ENregisterisimplementedwithasingleENABLEbit.ThisbitislogicallyORdwiththereset
inputtothemoduleandisfannedouttoalllogicalblockswithintheperipheral.
2.3.9.3SoftwareShutdownDetails
Powerconsumptionmustbeminimizedforalllogicalblocksthatareinshutdown.Inadditiontosimply
assertingtheappropriateresetsignaltoeachlogicalblockwithintheperipheral,clocksaregatedofftothe
correspondinglogicalblockaswell.Clocksareallowedtorunfor32clockcycles,whichisnecessaryto
fullyreseteachlogicalblock.Whentheappropriatelogicalblockisfullyreset,theclockinputtothat
subblockisgatedoff.
Whenablockisdisabled,theresetcontrolblockturnsofftheperipheralwiththefollowingsequence:
1.DeassertGBL_ENsignalorappropriateBLKn_ENsignal,whicheffectivelyresetsallsubblocksorthe
givensubblock.
2.Wait32clockcyclestoguaranteefullreset.
3.Gatetheinputclocktothelogicalblock(s).Whenthefullshutdownprocedureiscomplete,the
BLKn_EN_STATbitsand/ortheGBL_EN_STATbitcontain0.
Theoppositeisdoneforsoftwarecontrolledenablingofalogicalblock:
1.AsserttheBLK_ENsignaltoreleasethelogicalblockfromreset.
2.Turnonthelogicalblock.Whenthefullstart-upprocedureiscomplete,theBLKn_EN_STATbits
and/ortheGBL_EN_STATbitcontain1.
WhenusingtheGBL_ENtoshutdown/resettheperipheral,itisimportanttofirststopallmaster-initiated
commandsontheDMAbusinterface.Forexample,iftheGBL_ENisassertedinthemiddleofaDMA
transferfromtheperipheral,thebuscouldhang.Theprocedureisasfollows:
1.StopallRapidIOsourcetransactions,includingLSUandTXUoperations.Thisessentiallymeans
waitingfortheLSUorTXUCCfieldtobeset,or,alternatively,teardownoftheactiveTXUqueues.
2.DisablethePERENbitofthePCRregistertostopallnewlogicallayertransactions.
3.WaitthenumberofclockcyclesrequiredtofinishanycurrentDMAtransfer.
4.DeassertGBL_EN.
2.3.10Emulation
ExpectedbehaviorduringemulationhaltiscontrolledwithintheperipheralbythePeripheralControl
register(PCR).Thisisasingleglobalregisterthatcontrolsemulationforthewholeperipheral.
Figure39.EmulationControl(PeripheralControlRegisterPCR0x0004)
313210
ReservedPERENSOFTFREE
R-0R/W-0R/W-0R/W-1
LEGEND:R=Read,W=Write,n=valueatreset
68SerialRapidIO(SRIO)SPRU976–March2006
SubmitDocumentationFeedback