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InterruptConditions
Theinterruptconditionsareprogrammabletoselecttheinterruptoutputthatwillbedriven.Eachcondition
isindependentlyprogrammabletouseanyoftheinterruptdestinationssupportedbythedevice.For
example,aquadcoredevicemaysupportfourCPUservicinginterruptdestinations,onepercore
(INTDST0forCore0,INTDST1forCore1,INTDST2forCore2,andINTDST3forCore3).Inaddition,
INTDST4maybegloballyroutedtoallcoresandprovidenotificationofachangeintheErrorStatus
interruptICSR.INTDST5maybegloballyroutedtoallcoresandprovidenotificationofachangeinthe
DeviceResetinterruptICSR.Theroutingdefaultsareshownbelow.
Table27.InterruptConditionRoutingOptions
FieldAccessResetValueValueFunction
ICRxR0000b0000bRoutedtoINTDST0
0001bRoutedtoINTDST1
0010bRoutedtoINTDST2
0011bRoutedtoINTDST3
0100bRoutedtoINTDST4
0101bRoutedtoINTDST5
0110bRoutedtoINTDST6
0111bRoutedtoINTDST7
1111bNointerruptdestination,interruptsourcedisabled
otherReserved
Figure51.Doorbell0InterruptConditionRoutingRegisters
DOORBELL0_ICRR(AddressOffset0x280)
3128272423201916
ICR7ICR6ICR5ICR4
R/W-0000R/W-0000R/W-0000R/W-0000
15121187430
ICR3ICR2ICR1ICR0
R/W-0000R/W-0000R/W-0000R/W-0000
LEGEND:R=Read,W=Write,n=valueatreset
DOORBELL0_ICRR2(AddressOffset0x284)
3128272423201916
ICR15ICR14ICR13ICR12
R/W-0000R/W-0000R/W-0000R/W-0000
15121187430
ICR11ICR10ICR9ICR8
R/W-0000R/W-0000R/W-0000R/W-0000
LEGEND:R=Read,W=Write,n=valueatreset
OtherICRRshavethesamebitfieldmap,withthefollowingaddresses:
•DOORBELL1_ICRRandDOORBELL1_ICCR2(AddressOffset0x0290and0x0294)
•DOORBELL2_ICRRandDOORBELL2_ICRR2(AddressOffset0x02A0and0x02A4)
•DOORBELL3_ICRRandDOORBELL3_ICRR2(AddressOffset0x02B0and0x02B4)
•RXCPPI_ICRRandRXCPPI_ICRR2(AddressOffset0x02C0and0x02C4)
•TXCPPI_ICRRandTXCPPI_ICRR2(AddressOffset0x02D0and0x02D4)
SPRU976–March2006SerialRapidIO(SRIO)81
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