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Mailbox 1...64
from RapidIO Packet
Header - Received on any
input port
Mailbox Mapper
Q15
Q2 Q1
Q0
Queue assignable to any core
Packet Sequence
Message
n A
Packet
Manager
n+1 B
n+2 B
n+3 C
n+4 D
n+5 B
n+6
E
Buffer Descriptor
Queues:
Descriptor per Message
All Priorities
Dedicated Single Segment
Message Descriptor Queue
A
C
E
D
null
null
B
Multi-Segment Message
Descriptor Queue
Multi-Segment Message
Descriptor Queue N
L2 Memory
Data Buffer up to 256B
n Data Packet
n+3 Data Packet
n+4 Data Packet
n+6 Data Packet
256B Free Buffer
L2 Memory
Data Buffer up to 4K
n+5 Data Packet
n+2 Data Packet
n+1 Data Packet
4KB Free Buffer
acklD rsv prio tt ftype
ftype = 1011
destID
sourcelD msglen ssize msgseg/xmbox double-word 0 double-word 1 ...
double-word n-2 double-word n-1 CRC
PHY
LOG
TRA
LOG
TRAPHY
5 3 2 2 4 8 8 4 4 4 64 64
(n-4)*64
64 64 16
16n*64+16164210
n*64+64
letter
2
mbox
2
SRIOFunctionalDescription
2.3.4.1RXOperation
AsmessagepacketsarereceivedbytheRapidIOports,thedatamustbewrittenintomemorywhile
maintainingaccuratestateinformationthatisneededforfutureprocessing.Forinstance,ifamessage
spansmultiplepackets,informationmustbesavedthatallowsre-assemblyofthosepacketsbytheCPU.
TheCPPImoduleprovidesaschemefortrackingsingleandmulti-packetmessages,linkingmessagesin
queues,andgeneratinginterrupts.Figure14illustratesthescheme.
Figure14.CPPIRXSchemeforRapidIO
Messagesaddressedtoanyofthe64mailboxlocationscanbereceivedonanyoftheRapidIOports
simultaneously.Packetsarehandledsequentiallyinorderofreceipt.Thefunctionofthemailboxmapper
blockistodirecttheinboundmessagestotheappropriatequeueandfinallytothecorrectcore.The
queuemappingisprogrammableandmustbeconfiguredafterdevicereset.RapidIOoriginallysupported
only4mailboxeswith4letters/mailbox.Lettersallowconcurrentmessagetrafficbetweensenderand
receiver.However,formessagesthatconsistofonlysinglepackets,theunused4-bitpacketfieldnormally
indicatingthemessagesegmentextendstheavailablenumberofmailboxes.Figure15showsthepacket
headerfieldsformessagerequests.
Figure15.MessageRequestPacket
SPRU976–March2006SerialRapidIO(SRIO)41
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