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Descriptor
Descriptor
Buffer
Buffer
Port Rx DMA
State
Rx Queue Head Descriptor
Pointer
SRIOFunctionalDescription
Figure24.RXBufferDescriptor
TXBufferDescriptor
TX_DESCP0_0->TXDESC0=CSL_FMK(SRIO_TXDESC0_N_POINTER,(int)TX_DESCP0_1);
//linktoTX_DESCP0_1
//NDP
TX_DESCP0_0->TXDESC1=CSL_FMK(SRIO_TXDESC1_B_POINTER,(int)&xmtBuff1[0]);
//BufferPointer
TX_DESCP0_0->TXDESC2=CSL_FMK(SRIO_TXDESC2_DESTID,0xBEEF)|
CSL_FMK(SRIO_TXDESC2_PRI,1)|
CSL_FMK(SRIO_TXDESC2_TT,1)|
CSL_FMK(SRIO_TXDESC2_PORTID,3)|
CSL_FMK(SRIO_TXDESC2_SSIZE,SSIZE_256B)|
CSL_FMK(SRIO_TXDESC2_MAILBOX,0);
TX_DESCP0_0->TXDESC3=CSL_FMK(SRIO_TXDESC3_SOP,1)|
CSL_FMK(SRIO_TXDESC3_EOP,1)|
CSL_FMK(SRIO_TXDESC3_OWNERSHIP,1)|
CSL_FMK(SRIO_TXDESC3_EOQ,1)|
CSL_FMK(SRIO_TXDESC3_TEARDOWN,0)|
CSL_FMK(SRIO_TXDESC3_RETRY_COUNT,0)|
CSL_FMK(SRIO_TXDESC3_CC,0)|
CSL_FMK(SRIO_TXDESC3_MESSAGE_LENGTH,MLEN_512DW);
TX_DESCP0_1->TXDESC0=CSL_FMK(SRIO_TXDESC0_N_POINTER,0);
//endofmessage
//pollmode,extendedaddresstype2,5,6
TX_DESCP0_1->TXDESC1=CSL_FMK(SRIO_TXDESC1_B_POINTER,(int)&xmtBuff2[0]);
//32bit=type2,5,6.24bit=type8
TX_DESCP0_1->TXDESC2=CSL_FMK(SRIO_TXDESC2_DESTID,0xBEEF)|
CSL_FMK(SRIO_TXDESC2_PRI,1)|
CSL_FMK(SRIO_TXDESC2_TT,1)|
CSL_FMK(SRIO_TXDESC2_PORTID,3)|
CSL_FMK(SRIO_TXDESC2_SSIZE,SSIZE_256B)|
CSL_FMK(SRIO_TXDESC2_MAILBOX,1);
TX_DESCP0_1->TXDESC3=CSL_FMK(SRIO_TXDESC3_SOP,1)|
CSL_FMK(SRIO_TXDESC3_EOP,1)|
CSL_FMK(SRIO_TXDESC3_OWNERSHIP,1)|
CSL_FMK(SRIO_TXDESC3_EOQ,1)|
CSL_FMK(SRIO_TXDESC3_TEARDOWN,0)|
CSL_FMK(SRIO_TXDESC3_RETRY_COUNT,0)|
CSL_FMK(SRIO_TXDESC3_CC,0)|
CSL_FMK(SRIO_TXDESC3_MESSAGE_LENGTH,MLEN_512DW);
SPRU976–March2006SerialRapidIO(SRIO)57
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