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DMA Example
The desired operation is to send a Type 8 maintenance request
to an external device. The goal is to read 16B of RapidIO MMR
from an external device, starting offset 0x0000. This operation
involves the LSU block and utilizes the DMA for transferring the
response packet payload.
RapidIO defined bit positions
A0 A1 A2 A3
310
MMR offset 0x0000
B0
B1 B2 B3
MMR offset 0x0004
C0
C1 C2 C3
MMR offset 0x0008
D0
D1 D2 D3
MMR offset 0x000C
RapidIO
defined
MMR
offsets
A0A1A2A3B0B1B2B3 C0C1C2C3D0D1D2D3
Header fields
Type 8
Response
A0
A1 A2 A3
Byte
lane 3
Byte
Byte
lane 0
L2 offset 0x0
B0
B1 B2 B3
L2 offset 0x4
C0 C1 C2 C3
L2 offset 0x8
D0
D1 D2 D3
L2 offset 0xC
Big Endian
Little Endian
A3
A2 A1 A0
Byte
lane 3lane 0
L2 offset 0x0
B3
B2 B1 B0
L2 offset 0x4
C3 C2 C1 C0
L2 offset 0x8
D3
D2 D1 D0
L2 offset 0xC
Double-word0 Double-word1
SRIOFunctionalDescription
Figure30.DMAExample
2.3.9Reset
TheRapidIOperipheralallowsindependentsoftwarecontrolledshutdownforthefollowingblocks:
SERDESTXandRXindividualportsandPLL,channelizeddatapathlogic(8b/10b,ratehandoffFIFO,
CRClogic,lanestriping/de-skewlogic),CPPImodule,LSUmodule,MAUmodule,andMMRregisters.
WiththeexceptionofBLK_EN0fortheMMRregisters,whentheBLKn_ENsignalsaredeasserted,the
clocksaregatedtotheseblocks,effectivelyprovidingashutdownfunction.
ResetoftheSERDESmacrosishandledindependentlyoftheregistersdiscussedinthissection.The
SERDEScanbeconfiguredtoshutdownunusedlinksorfullyshutdown.SERDESTXandRXchannels
maybeenabled/disabledbywritingtobit0oftheSERDES_CFGTXn_CNTLand
SERDES_CFGRXn_CNTLregisters.ThePLLandremainingSERDESfunctionalblockscanbecontrolled
bywritingtotheENPLLsignalsinthePER_SET_CNTLorSERDES_CFGn_CNTLregister,dependingon
deviceimplementation.TheseregisterswilldrivetheSERDESsignalinputs,whichwillgatethereference
clocktotheseblocksinternally.Thisreferenceclockissourcedfromadevicepinspecificallyforthe
SERDESandisnotderivedfromtheCPUclock,thusitresetsasynchronously.ENPLLwilldisableall
SERDEShigh-speedoutputclocks.Sincetheseclocksaredistributedtoallthelinks,ENPLLshouldonly
beusedtocompletelyshutdowntheperipheral.ItshouldbenotedthatshutdownofSERDESlinksin
betweennormalpackettransmissionsisnotpermissiblefortworeasons.First,theserialRapidIOsends
idlepacketsbetweendatapacketstomaintainsynchronizationandlanealignment.Withoutthis
mechanism,theRapidIORXlogiccanbemis-alignedforboth1Xand4Xports.Second,thelocktimeof
theSERDESPLLwouldneedtoreoccur,whichwouldslowdowntheoperation.
Allchip-IOsignalsmustberesetasynchronouslytoaknownstate.WhentheSERDESENTXsignalis
heldlow,thecorrespondingtransmitterispowereddown.Inthisstate,bothoutputs,TXPandTXN,willbe
pulledhightoVDDT.
64SerialRapidIO(SRIO)SPRU976–March2006
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