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SRIOFunctionalDescription
Figure34.BLK0_EN_STAT(Address0x003C)
3110
ReservedEN_STAT
R-0R-1
LEGEND:R=Read,W=Write,n=valueatreset
Figure35.BLK1_EN(Address0x0040)
3110
ReservedEN
R-0R/W-1
LEGEND:R=Read,W=Write,n=valueatreset
Figure36.BLK1_EN_STAT(Address0x0044)
3110
ReservedEN_STAT
R-0R-1
LEGEND:R=Read,W=Write,n=valueatreset
•
•
•
Figure37.BLK8_EN(Address0x0078)
3110
ReservedEN
R-0R/W-1
LEGEND:R=Read,W=Write,n=valueatreset
Figure38.BLK8_EN_STAT(Address0x007C)
3110
ReservedEN_STAT
R-0R-1
LEGEND:R=Read,W=Write,n=valueatreset
Table24.EnableandEnableStatusBitFieldDescriptions
NameBitAccessDescription
GBL_EN0R/WControlsresettoallclockdomainswithintheperipheral.
0=Peripheraltobedisabled(heldinreset,clocksdisabled)
1=Peripheraltobeenabled
GBL_EN_STAT0-9RIndicatesstateofGBL_ENresetsignal.
0=Peripheralinresetandallclocksareoff
1=Peripheralenabledandclocking
BLK0_EN0R/WControlsresetto0thclock/logicaldomain.Byconvention,BLK0shouldalwaysbe
theMMRPeripheralcontrolregisters.
0=Logicalblock0tobedisabled
1=Logicalblock0tobeenabled
BLK0_EN_STAT0RIndicatesstateofBLK0_ENresetsignal.
0=Logicalblock0disabled
1=Logicalblock0enabled
66SerialRapidIO(SRIO)SPRU976–March2006
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