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5.15SERDESMacroConfigurationRegistern(SERDES_CFGn_CNTL)
SRIORegisters
Therearefouroftheseregisters,tosupportfourports.
Figure71.SERDESMacrosCFG(0-3)Registers(SERDES_CFGn_CNTL)
3116
Reserved
R-0
1514131211109876543210
ReservedLBReservedMPYENPLL
R-0R/W-0R-0R/W-0R/W-0
LEGEND:R=Read,W=Write,n=valueatreset
Table45.SERDESMacrosCFG(0-3)Registers(SERDES_CFGn_CNTL)FieldDescriptions
BitFieldValueDescription
31:10ReservedReserved.
9:8LBLoopbandwidth.Specifyloopbandwidthsettings.
00Frequencydependentbandwidth.ThePLLbandwidthissettoatwelfthofthefrequencyof
RIOCLK/RIOCLK.
01Reserved
10Lowbandwidth.ThePLLbandwidthissettoatwentiethofthefrequencyofRIOCLK/RIOCLK,or
3MHz(whicheverislarger).
11Highbandwidth.ThePLLbandwidthissettoaeighthofthefrequencyofRIOCLK/RIOCLK.
7:6ReservedReserved.
5:1MPYPLLmultiply.SelectPLLmultiplyfactorsbetween4and60.
00004x
00015x
00106x
0011Reserved
01008x
010110x
011012x
011112.5x
100015x
100120x
101025x
1011Reserved
1100Reserved
110150x
111060x
1111Reserved
0ENPLLEnablePLL.EnablesthePLL.
SerialRapidIO(SRIO) 116SPRU976–March2006
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