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SRIORegisters
Table40.SERDESReceiveChannelConfigurationRegistersn(SERDES_CFGRXn_CNTL)Field
Descriptions(continued)
BitFieldValueDescription
11ReservedReserved.
10:8TERMTermination.SelectsinputterminationoptionssuitableforavarietyofACorDCcoupled
scenarios.
000CommonpointconnectedtoVDDT.ThisconfigurationisforDCcoupledsystemsusingCML
transmitters.Thecommonmodevoltageisdeterminedjointlybyboththereceiverandthe
transmitter.Commonmodeterminationisviaa50pFcapacitortoVSSA.
001Commonpointsetto0.8VDDT.ThisconfigurationisforACcoupledsystemsusingCML
transmitters.Thetransmitterhasnoeffectonthereceivercommonmode,whichissettooptimize
theinputsensitivityofthereceiver.Commonmodeterminationisviaa50pFcapacitortoVSSA.
010Reserved
011Commonpointfloating.ThisconfigurationisforDCcoupledsystemsthatrequirethecommon
modevoltagetobedeterminedbythetransmitteronly.ThesearetypicallynotCML.Common
modeterminationisviaa50pFcapacitortoVSSA.
1xxReserved
7INVPAIRInvertpolarity.InvertspolarityofRXPIandRXNn.
0Normalpolarity.RXPnconsideredtobepositivedataandRXNinegative.
1Invertedpolarity.RXPnconsideredtobenegativedataandRXNnpositive.
6:5RATEOperatingrate.Selectsfull,halforquarterrateoperation.
00Fullrate.TwodatasamplestakenperPLLoutputclockcycle.
01Halfrate.OnedatasampletakenperPLLoutputclockcycle.
10Quarterrate.OnedatasampletakeneverytwoPLLoutputclockcycles.
11Reserved
4:2BUS-Buswidth.Selectsthewidthoftheparallelinterface(10or8bit).
WIDTH
00010-bitoperation.DataisoutputonRDn[9:0].RXBCLK[n]periodis10bitperiods(4high,6low).
0018-bitoperation.DataisoutputonRDn[7:0].RXBCLK[n]periodis8bitperiods(4high,4low).
RDn[9:8]willreplicatebits[1:0]fromthepreviousbyte.
01xReserved
1xxReserved
1ReservedReserved,keepaszeroduringwritestothisregister.
0ENRXEnablereceiver.Enablesthisreceiverwhenhigh.
0Disable
1Enable
Table41.EQBits
CFGRX[22:19]LowFreqGainZeroFreq(ate
28
(min))
0000Maximum-
0001AdaptiveAdaptive
001xReserved
01xxReserved
1000Adaptive1084MHz
1001805MHz
1010573MHz
1011402MHz
1100304MHz
1101216MHz
1110156MHz
1111135MHz
SPRU976–March2006SerialRapidIO(SRIO)113
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