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SRIOFunctionalDescription
Table8.BitsofSERDES_CFGRXn_CNTLRegisters(continued)
BitFieldValueDescription
15:14LOSLossofsignal.Enableslossofsignaldetectionwith2selectablethresholds.
00Disabled.Lossofsignaldetectiondisabled.
01Highthreshold.Lossofsignaldetectionthresholdintherange85to195mV
dfpp
.Thissettingis
suitableforInfiniband.
10Lowthreshold.Lossofsignaldetectionthresholdintherange65-175mV
dfpp
.Thissettingis
suitableforPCI-EandS-ATA.
11Reserved
13:12ALIGNSymbolalignment.Enablesinternalorexternalsymbolalignment.
00Alignmentdisabled.Nosymbolalignmentwillbeperformedwhilethissettingisselected,or
whenswitchingtothisselectionfromanother.
01Commaalignmentenabled.Symbolalignmentwillbeperformedwheneveramisalignedcomma
symbolisreceived.
10Alignmentjog.Thesymbolalignmentwillbeadjustedbyonebitpositionwhenthismodeis
selected(i.e.,CFGRX[13:12]changesfrom0xto1x).
11Reserved
11ReservedReserved.
10:8TERMTermination.SelectsinputterminationoptionssuitableforavarietyofACorDCcoupled
scenarios.
000CommonpointconnectedtoVDDT.ThisconfigurationisforDCcoupledsystemsusingCML
transmitters.Thecommonmodevoltageisdeterminedjointlybyboththereceiverandthe
transmitter.Commonmodeterminationisviaa50pFcapacitortoVSSA.
001Commonpointsetto0.8VDDT.ThisconfigurationisforACcoupledsystemsusingCML
transmitters.Thetransmitterhasnoeffectonthereceivercommonmode,whichissetto
optimizetheinputsensitivityofthereceiver.Commonmodeterminationisviaa50pFcapacitor
toVSSA.
010Reserved
011Commonpointfloating.ThisconfigurationisforDCcoupledsystemsthatrequirethecommon
modevoltagetobedeterminedbythetransmitteronly.ThesearetypicallynotCML.Common
modeterminationisviaa50pFcapacitortoVSSA.
1xxReserved
7INVPAIRInvertpolarity.InvertspolarityofRXPnandRXNn.
0Normalpolarity.RXPnconsideredtobepositivedataandRXNnnegative.
1Invertedpolarity.RXPnconsideredtobenegativedataandRXNnpositive.
6:5RATEOperatingrate.Selectsfull,halforquarterrateoperation.
00Fullrate.TwodatasamplestakenperPLLoutputclockcycle.
01Halfrate.OnedatasampletakenperPLLoutputclockcycle.
10Quarterrate.OnedatasampletakeneverytwoPLLoutputclockcycles.
11Reserved
4:2BUS-Buswidth.Selectsthewidthoftheparallelinterface(10or8bit).
WIDTH
00010-bitoperation.DataisoutputonRDn[9:0].RXBCLK[n]periodis10bitperiods(4high,6low).
0018-bitoperation.DataisoutputonRDn[7:0].RXBCLK[n]periodis8bitperiods(4high,4low).
RDn[9:8]willreplicatebits[1:0]fromthepreviousbyte.
01xReserved
1xxReserved
1ReservedReserved,keepaszeroduringwritestothisregister.
0ENRXEnablereceiver.Enablesthisreceiverwhenhigh.
0Disable
1Enable
SPRU976–March2006SerialRapidIO(SRIO)29
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