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InterruptConditions
WhereICS0-TXCPPIinterrupt,bufferdescriptorqueue0,throughICS15-TXCPPIinterrupt,buffer
descriptorqueue15.
ClearingofanyICSRbitisdependentontheCPUwritingtotheTXDMAStateCP.TheCPU
acknowledgestheinterruptafterreclaimingallavailablebufferdescriptorsbywritingtheCPvalue.This
valueiscomparedagainsttheportwrittenvalueintheTXDMAStateCPregister.Ifequal,theinterruptis
deasserted.
Figure49.LSULoad/StoreModuleInterrupts
LSUInterruptConditionStatusRegisters(ICSR)(AddressOffset0x0260)
31302928272625242322212019181716
ICS31ICS30ICS29ICS28ICS27ICS26ICS25ICS24ICS23ICS22ICS21ICS20ICS19ICS18ICS17ICS16
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
1514131211109876543210
ICS15ICS14ICS13ICS12ICS11ICS10ICS9ICS8ICS7ICS6ICS5ICS4ICS3ICS2ICS1ICS0
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND:R=Read,W=Write,n=valueatreset
LSUInterruptConditionClearRegisters(ICCR)(AddressOffset0x0268)
31302928272625242322212019181716
ICC31ICC30ICC29ICC28ICC27ICC26ICC25ICC24ICC23ICC22ICC21ICC20ICC19ICC18ICC17ICC16
W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0
1514131211109876543210
ICC15ICC14ICC13ICC12ICC11ICC10ICC9ICC8ICC7ICC6ICC5ICC4ICC3ICC2ICC1ICC0
W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0W-0
LEGEND:R=Read,W=Write,n=valueatreset
Where:
•Bit0-Transactioncomplete,NoErrors(Posted/Non-posted),LSU1–seenote
•Bit1-Non-postedtransactionreceivedERRORresponse,orerrorinresponsepayload,LSU1
•Bit2-TransactionwasnotsentduetoXoffcondition,LSU1
•Bit3-TransactionwasnotsentduetounsupportedtransactiontypeorinvalidfieldencodingLSU1
•Bit4-TransactionTimeoutOccurred,LSU1
•Bit5-TransactionwasnotsentduetoDMAdatatransfererror,LSU1
•Bit6-RetryDoorbellresponsereceivedorAtomicTest-and-swapwasnotallowed(semaphoreinuse),
LSU1
•Bit7-Packetnotsentduetounavailableoutboundcreditatgivenpriority,LSU1
•Bit8-Transactioncomplete,NoErrors(Posted/Non-posted),LSU2–seenote
•Bit9-Non-postedtransactionreceivedERRORresponse,orerrorinresponsepayload,LSU2
•Bit10-TransactionwasnotsentduetoXoffcondition,LSU2
•Bit11-TransactionwasnotsentduetounsupportedtransactiontypeorinvalidfieldencodingLSU2
•Bit12-TransactionTimeoutOccurred,LSU2
•Bit13-TransactionwasnotsentduetoDMAdatatransfererror,LSU2
•Bit14-RetryDoorbellresponsereceivedorAtomicTest-and-swapwasnotallowed(semaphorein
use),LSU2
•Bit15-Packetnotsentduetounavailableoutboundcreditatgivenpriority,LSU2
•Bit16-Transactioncomplete,NoErrors(Posted/Non-posted),LSU3–seenote
•Bit17-Non-postedtransactionreceivedERRORresponse,orerrorinresponsepayload,LSU3
•Bit18-TransactionwasnotsentduetoXoffcondition,LSU3
•Bit19-TransactionwasnotsentduetounsupportedtransactiontypeorinvalidfieldencodingLSU3
•Bit20-TransactionTimeoutOccurred,LSU3
SPRU976–March2006SerialRapidIO(SRIO)79
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