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4.4InterruptStatusDecodeRegisters
InterruptConditions
Figure53.Error,Reset,andSpecialEventInterruptConditionRoutingRegisters
ERR_RST_EVNT_ICRR(AddressOffset0x02F0)
31121187430
ReservedICR2ICR1ICR0
R-0R/W-0000R/W-0000R/W-0000
LEGEND:R=Read,W=Write,n=valueatreset
ERR_RST_EVNT_ICRR2(AddressOffset0x02F4)
3116
Reserved
R-0
15121187430
ICR11ICR10ICR9ICR8
R/W-0000R/W-0000R/W-0000R/W-0000
LEGEND:R=Read,W=Write,n=valueatreset
ERR_RST_EVNT_ICRR3(AddressOffset0x02F8)
31430
ReservedICR16
R-0R/W-0000
LEGEND:R=Read,W=Write,n=valueatreset
Thereare8blocksoftheICSRstoindicatethesourceofapendinginterrupt.
0x0200:Doorbell0interrupts
0x0210:Doorbell1interrupts
0x0220:Doorbell2interrupts
0x0230:Doorbell3interrupts
0x0240:RxCPPIinterrupts
0x0250:TxCPPIinterrupts
0x0260:LSUinterrupts
0x0270:Error,Reset,andSpecialEventinterrupts
Toreducethenumberofreads(upto5reads)requiredtofindthesourcebit,anInterruptStatusDecode
Register(ISDR)isimplementedforeachsupportedphysicalinterrupt(INTDST0–INTDST7).These
registersareshowninFigure56.Interruptsourcesthatselectaparticularphysicalinterruptdestination
aremappedtospecificbitsinthedecoderegister.Theinterruptsourcesareonlymappedtoaninterrupt
decoderegisteriftheICRRroutestheinterruptsourcetothecorrespondingphysicalinterrupt.Thestatus
decodebitisalogicalORofmultipleinterruptsourcesthataremappedtothesamebit.Themappingof
interruptsourcebitstodecodebitsisfixedandnon-programmable,asfollows:
SPRU976–March2006SerialRapidIO(SRIO)83
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