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ListofFigures
1RapidIOArchitecturalHierarchy..........................................................................................15
2RapidIOInterconnectArchitecture.......................................................................................16
3SerialRapidIODevicetoDeviceInterfaceDiagrams.................................................................17
4SRIOPeripheralBlockDiagram..........................................................................................20
5OperationSequence.......................................................................................................21
61x/4xRapidIOPacketDataStream(Streaming-WriteClass)........................................................22
7SerialRapidIOControlSymbolFormat..................................................................................22
8SRIOConceptualBlockDiagram........................................................................................25
9Load/StoreDataTransferDiagram......................................................................................32
10Load/StoreRegistersforRapidIO(AddressOffset:LSU10x400-0x418,LSU20x420-0x438,LSU3
0x440-0x458,LSU40x460-0x478).......................................................................................33
11LSURegistersTiming.....................................................................................................35
12ExampleBurstNWRITE_R...............................................................................................36
13Load/StoreModuleDataFlow............................................................................................37
14CPPIRXSchemeforRapidIO............................................................................................41
15MessageRequestPacket.................................................................................................41
16QueueMappingTable(AddressOffset:0x0800-0x08FC)..........................................................42
17QueueMappingRegisterRXU_MAP_Ln...............................................................................43
18QueueMappingRegisterRXU_MAP_Hn...............................................................................43
19RXBufferDescriptorFields...............................................................................................44
20RXCPPIModeExplanation..............................................................................................47
21CPPIBoundaryDiagram..................................................................................................48
22TXBufferDescriptorFields...............................................................................................49
23WeightedRoundRobinProgrammingRegisters(AddressOffset0x7E0–0x7EC)..............................52
24RXBufferDescriptor.......................................................................................................57
25TXBufferDescriptor.......................................................................................................58
26DoorbellOperation.........................................................................................................59
27FlowControlTableEntryRegisters(AddressOffset0x0900-0x093C)............................................61
28TransmitSourceFlowControlMasks...................................................................................62
29ConfigurationBusExample...............................................................................................63
30DMAExample..............................................................................................................64
31GBL_EN(Address0x0030)...............................................................................................65
32GBL_EN_STAT(Address0x0034).......................................................................................65
33BLK0_EN(Address0x0038)..............................................................................................65
34BLK0_EN_STAT(Address0x003C).....................................................................................66
35BLK1_EN(Address0x0040)..............................................................................................66
36BLK1_EN_STAT(Address0x0044).....................................................................................66
37BLK8_EN(Address0x0078)..............................................................................................66
38BLK8_EN_STAT(Address0x007C).....................................................................................66
39EmulationControl(PeripheralControlRegisterPCR0x0004).......................................................68
40BootloadOperation........................................................................................................72
41DetectableErrors...........................................................................................................73
42RapidIODOORBELLPacketforInterruptUse.........................................................................74
43DOORBELL0InterruptRegistersforDirectI/OTransfers............................................................76
44DOORBELL1InterruptRegistersforDirectI/OTransfers............................................................76
45DOORBELL2InterruptRegistersforDirectI/OTransfers............................................................77
46DOORBELL3InterruptRegistersforDirectI/OTransfers............................................................77
47RX_CPPIInterruptsUsingMessagingModeDataTransfers........................................................78
48TX_CPPIInterruptsUsingMessagingModeDataTransfers........................................................78
49LSULoad/StoreModuleInterrupts.......................................................................................79
50ERR_RST_EVNTError,Reset,andSpecialEventInterrupt.........................................................80
51Doorbell0InterruptConditionRoutingRegisters......................................................................81
6ListofFiguresSPRU976–March2006
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