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SRIOFunctionalDescription
Segmentation:
TheLSUhandlestwotypesofsegmentationofoutboundrequests.ThefirsttypeiswhentheByte_Count
ofRead/Writerequestsexceeds256bytes(upto4KB).ThesecondtypeiswhenRead/Writerequest
RapidIOaddressisnon-64baligned.Inbothcases,theoutgoingrequestmustbebrokenupintomultiple
RapidIOrequestpackets.Forexample,assumethattheCPUwantstoperforma1KBstoreoperationto
anexternalRapidIOdevice.AftersettinguptheLSUregisters,theCPUperformsonewritetothe
LSU_Reg5register.TheperipheralhardwarethensegmentsthestoreoperationintofourRapidIOwrite
packetsof256Beach,andcalculatesthe64b-alignedRapidIOaddress,WRSIZE,andWDPTRas
requiredforeachpacket.ThisexamplerequiresfouroutboundhandlestobeassignedandfourDMA
transmitrequests.TheLSUregisterscannotbereleaseduntilallpostedrequestpacketsarepassedto
theTXFIFOs.Alternatively,fornon-postedoperations,suchasCPUloads,allpacketresponsesmustbe
receivedbeforetheLSUregistersarereleased.
2.3.3.3RXOperation
Responsepacketsarealwaystype13RapidIOpackets.Allresponsepacketswithtransactiontypesnot
equalto0001bareroutedtotheLSUblocksequentiallyinorderofreception.Thesepacketsmayhavea
payload,dependingonthetypeofcorrespondingrequestpacketthatwasoriginallysent.Duetothe
natureofRapidIOswitchfabricsystems,responsepacketscanarriveinanyorder.Thedatapayload,if
any,andheaderdataismovedfromtheRXFIFOtothesharedRXbuffer.TheDestIDfieldofthepacket
isexaminedtodeterminewhichcoreandcorrespondingsetofregistersarewaitingfortheresponse.
Remember,therecanbeonlyoneoutstandingrequestpercore.Anypayloaddataismovedfromthe
sharedRXbufferpoolintomemorythroughnormalDMAbusoperations.
Registersforallnon-postedoperationsshouldonlybeheldforafiniteamountoftimetoavoidblocking
resourceswhenarequestorresponsepacketissomehowlostintheswitchfabric.Thistimecorrelatesto
the24-bitPortResponseTime-outControlCSRvaluediscussedinsections5.10.1and6.1.2.4ofthe
serialspecification.Ifthetimeexpires,control/commandregisterresourcesshouldbereleased,andan
errorisloggedintheERRORMANAGEMENTRapidIOregisters.TheRapidIOspecificationstatesthatthe
maximumtimeinterval(all1s)isbetween3and6seconds.Alogicallayertimeoutoccursiftheresponse
packetisnotreceivedbeforeacountdowntimer(initializedtothisCSRvalue)reacheszero.
Eachoutstandingpacketresponsetimerrequiresa4-bitregister.Theregisterisloadedwiththecurrent
timecodewhenthetransactionissent.Eachtimethetimecodechanges,a4-bitcompareisdonetothe
register.Iftheregisterbecomesequaltothetimecodeagain,withoutaresponsebeingseen,thenthe
transactionhastimedout.Essentially,insteadofthe24-bitvaluerepresentingtheperiodoftheresponse
timer,theperiodisnowdefinedasP=(2^24x16)/F.Thismeansthecountdowntimerfrequencyneedsto
be44.7–89.5Mhzfora6–3secondresponsetimeout.Becausetheneededtimerfrequencyisderived
fromtheDMAbusclock(whichisdevicedependent),thehardwaresupportsaprogrammable
configurationregisterfieldtoproperlyscaletheclockfrequency.Thisconfigurationregisterfieldis
describedinthePeripheralSettingControlregister(Addressoffset0x0020).
IfaresponsepacketindicatesERRORstatus,theLoad/StoremodulenotifiestheCPUbygeneratingan
errorinterruptforthependingnon-postedtransaction.Iftheresponsehascompletedsuccessfully,andthe
InterruptReqbitissetinthecontrolregister,themodulegeneratesaCPUservicinginterrupttonotifythe
CPUthattheresponseisavailable.Thecontrol/commandregisterscanbereleasedassoonasthe
responsepacketisreceivedbythelogicallayer.Thehardwareisnotresponsibleforattemptinga
retransmissionofthenon-postedtransaction.
IfaDoorbellresponsepacketindicatesRetrystatus,theLoad/StoremodulenotifiestheCPUby
generatinganinterrupt.Thecontrol/commandregisterscanbereleasedassoonastheresponsepacket
isreceivedbythelogicallayer.Thehardwareisnotresponsibleforattemptingretransmissionofthe
Doorbelltransaction.
SPRU976–March2006SerialRapidIO(SRIO)39
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