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HIGHLIGHTS
computes the address and definition
of
the next
bus cycle during the current bus cycle. Address
pipelining exposes this advance information to
the memory subsystem, allowing one memory
bank to decode the next bus cycle while another
bank
is
responding to the current
cycle.
1.3
Virtual Memory Support
Virtual memory enables the maximum size
of
a
program,
or
a mix
of
programs, to be governed
by available disk space rather than the size
of
physical
(RAM)
memory, which
is
presently on
the order of
400 times more expensive. The
resulting flexibility benefits manufacturers (who
can supply multiple performance
levels
of a
product that differ only in memory configura-
tions), programmers (who can leave storage
management to the operating system, rather
than writing overlays), and end-users (who can
run more and larger applications without worry-
ing about running out of memory).
Virtual memory
is
implemented
by
an operating
system with support from the hardware. The
80386 supports virtual memory systems based
on segments
or
pages. Segment-based virtual
memory
is
appropriate for smaller 16-bit systems
whose segments are at most
64
kilobytes in
length. The 80386, however, supports segments
as
large as 4 gigabytes; therefore most large-scale
80386-based systems
will
base their virtual mem-
ory systems on the 80386's demand paging
facilities.
For
each page, the 80386 supplies the
Present, Dirty, and Accessed bits required to
efficiently implement demand-paged virtual mem-
ory.
The 80386 automatically traps to the oper-
ating system when an instruction refers to a not-
present page; when the operating system has
swapped the missing page in from disk, the
80386 automatically re-executes the instruction.
To
insure high virtual memory performance, the
80386
provides
an
associative
on-<:hip
cache for
paging information. The cache (called a trans-
lation lookaside buffer,
or
TLB) contains the
mapping information for the
32
most recently
1-3
used pages. 80386 pages are 4 kilobytes long;
by
mapping
128
kilobytes of memory at once, the
TLB enables the80386 to translate most addresses
on-chip without consulting a memory-based
page table.
In typical systems, 98-99%
of
address
references
will
"hit" a TLB entry.
1.4 Configurable Protection
Executing
3-4
million instructions per second,
the 80386 has the
"horsepower" to support
extremely sophisticated applications consisting
of
hundreds
or
thousands of program modules.
Insuch
applications, the question
is
not whether
there
will
be
bugs, but how they can
be
found
and eliminated as quickly
as
possible, and how
their damage can
be
tightly confined. These
applications can be debugged faster and made
more robust in production if the processor
verifies each instruction for conformance to
protection criteria. The degree and style of
protection that should
be
applied, however,
is
inherently application-specific. Indeed, simple
embedded real-time applications may work best
with no protection. A range
of
protection needs
is
best satisfied with a range
of
protection
facilities that can be employed selectively as can
those provided
by
the
80386:
o Separation of task address spaces;
o From zero to four privilege
levels;
'"
Privileged instructions (for example, Halt);
o Typed segments (for example, code
or
data);
'"
Access rights for segments and pages (for
example, read-only or execute-only);
'"
Segment limit checking.
All 80386 protection checks are performed in the
on-chip pipeline to maximize performance.
1.5 Extended Debugging Support
The 80386's four on-chip debug registers can also
significantly reduce program debugging time.
These registers operate independently
of
the