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80386
8EO#
L
H
L x
Ii
L L
8E2#
L
L x
H
L
H
L L
;(
L
H
H
x
x x
L
[~
A1
8E3# 8E1#
----
8EO#
L H L
8E1#
231630-8
K-map for A 1 signal (same as Figure 5-3)
8EO#
L H
L x L L L
8E2#
L
L x H L
H
H
L
·x
L
H
[~
8HE
8[3#
8E3#
--,,--~
8E1#
x x L x L
L H
L
8E1#
231630-9
K-map for 16-bit
SHE
# signal
8EO#
L H
L
x L H L
L
H
L x L
8LE#
(OR
AO)
8E2#
H
L L
X·
H
8E3#
H
x x H
.x
L
L H
L
8E1#
231630-10
K-map for 16-bit
SLE
# signal (same as
AO
signal in Figure 5-3)
Figure 5-7.
Logic
to
Generate A1,
BHE#
and
BLE#
for
16-Bit Buses
Table 5-8.
Transfer
Bus
Cycles
for
Bytes,
Words
and
Dwords
Byte-Length
of
Logical
Operand
1
2
4
Physical Byte Address xx
00
01
10
11
00
01
10
11
-in Memory (low-order bits)
Transfer Cycles over b w w
w
hb,* d
hb
hw, h3,
32-Bit Data Bus
Ib
13
Iw
Ib
Transfer Cycles over b w
Ib,
w
li,'\~~;
..
'
Ivv,
hb,
hw,
my",
16-Bit Data Bus
hb·
•.
...
hw
Ib,
Iw
hb;
.
JllVi
Ib
Key: b = byte transfer
3
= 3-byte transfer
w
= word transfer
d
= Dword transfer
I
= low-order portion
h
= high-order portion
m
= mid-order portion
x = don't care
=
B516#
asserted causes second bus cycle
'For
this case, 8086,
88,
186, 188, 286 transfer
Ib
first, then
hb.
71