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CLK2
[
(82384
ClK)
[
BED
# -
BE
1
#,
[
A2-
A31,
M/IO#,
D/c#
W/R# [
ADS# [
8S16 # [
READY#
[
lOCK#
[
DO-
D31
[
TlP
CYCLE
1
PIPELINED
(WRITE)
T2P
T2P
ASSERTING
NA#
MORE
THAN
ONCE
DURING
ANY
CYCLE
HAS
NO
ADDITIONAL
EFFECTS
T1P
80386
CYCLE
2
PIPELINED
(READ)
T2
T2P
NA#
COULD
HAVE
BEEN
ASSERTED
IN
Tl P
IF
DESIRED.
ASSERTION
NOW
IS
THE
LATEST
TIME
POSSIBLE
TO
ALLOW
80386
TO
ENTER
T2P
STATE
TO
MAINTAIN
PIPELINING
IN
CYCLE
3
TlP
CYCLE
3
PIPELINED
(WRITE)
121
T2P
11P
Figure 5-19. Details
of
Address Pipelining During Cycles with Wait States
83
CYCLE
4
PIPELINED
(READ)
231630-23