Intel 80386 DJ Equipment User Manual


 
inter
80386
8.2 INSTRUCTION ENCODING
8.2.1
Overview
All instruction encodings are subsets of the general
instruction format shown
in
Figure 8-1. Instructions
consist of one or two primary opcode bytes, possibly
an
address specifier consisting of the "mod rim"
byte and "scaled index" byte, a displacement if
re-
quired, and
an
immediate data field if required.
Within the primary opcode or opcodes, smaller
en-
coding fields may
be
defined. These fields vary ac-
cording to the class of operation. The fields define
such information as direction of the operation, size
of the
displacements, register encoding, or sign ex-
tension.
Almost all instructions referring
to
an
operand
in
memory have
an
addressing mode byte following
the primary opcode byte(s). This byte, the mod
rim
byte, specifies the address mode to
be
used. Certain
encodings of the
mod
rim byte indicate a second
addressing byte, the scale-index-base byte, follows
the mod
rim byte to fully specify the addressing
mode.
Addressing modes can
include a displacement
im-
mediately following the mod rim byte, or scaled in-
dex byte. If a displacement is present, the possible
sizes are
8,
16 or
32
bits.
If
the instruction specifies
an
immediate operand,
the immediate operand follows any
displacement
bytes. The immediate operand,
if
specified, is always
the last field of the instruction.
Figure
8-1
illustrates several of the fields that can
appear
in
an
instruction, such
as
the mod field and
the
rim field, but the Figure does not show all fields.
Several
smaller fields also appear
in
certain instruc-
tions, sometimes within the opcode bytes them-
selves. Table 8-2
is
a complete list of all fields ap-
pearing
in
the 80386 instruction set. Further ahead,
following Table
8-2,
are detailed tables for each
field.
ITTTTTTT
T I
TTT
TTTTT
I mod
TTT
rim I
ss
index base
Id32i16i8i
none
data32i16i8i
none
:z
07
o)~~~\
)
opcode
(one or two bytes)
(T
represents
an
opcode bit.)
"mod rim" "s-i-b"
byte byte
\~--------~--------~)
register and address
mode specifier
address
displacement
(4,
2,
1 bytes
or none)
Figure 8-1.
General
Instruction
Format
Table 8-2. Fields
within
80386
Instructions
Field Name
Description
w
Specifies if Data is Byte or
Full Size (Full Size
is
either 16 or
32
Bits
d Specifies Direction of Data Operation
s Specifies if
an
Immediate Data Field Must be Sign-Extended
reg
General Register Specifier
mod
rim
Address Mode Specifier (Effective Address can
be
a General Register)
ss
Scale Factor for Scaled Index Address Mode
index
General Register to
be
used as Index Register
base
General Register to
be
used as Base Register
sreg2
Segment Register Specifier for
CS,
SS,
OS,
ES
sreg3 Segment Register Specifier for
CS,
SS,
OS,
ES,
FS,
GS
tttn For Conditional Instructions, Specifies a Condition Asserted
or a Condition Negated
Note: Table
8-1
shows encoding of individual instructions.
125
immediate
data
(4,
2,
1 bytes
or none)
Number
of
Bits
1
1
1
3
2 for mod;
3 for
rim
2
3
3
2
3
4