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80386
80386
I/O
cycles automatically generated for co-
processor communication do not require BS16# be
asserted. The coprocessor type, 80287 or 80387,
is
sensed
on
the ERROR# input shortly after the faIl-
ing
edge of
RESET.
The 80386 transfers only 16-bit
quantities between itself and the 80287, but must
transfer 32-bit quantities between itself
and
the
80387. Therefore, BS16#
is
a don't care during
80287
cycles and
must
not
be asserted during
80387 communication
cycles.
5.2.7 Bus Arbitration Signals
5.2.7.1
INTRODUCTION
This section describes the mechanism
by
which the
processor relinquishes
control of its local buses
when
requested by another
bus
master device. See
5.5.1
Entering and Exiting Hold Acknowledge for
additional information.
5.2.7.2
BUS
HOLD REQUEST (HOLD)
This input indicates some device other than the
80386 requires bus mastership.
HOLD must remain asserted
as
long
as
any other
device
is
a local
bus
master. HOLD
is
not recognized
while
RESET
is asserted. If RESET
is
asserted while
HOLD
is asserted, RESET
has
priority
and
places
the
bus
into
an
idle state, rather than the hold ac-
knowledge
(high impedance) state.
HOLD
is level-sensitive and
is
a synchronous input.
HOLD
signals must always meet setup and hold
times
t23
and
t24
for correct operation.
5.2.7.3 BUS HOLD ACKNOWLEDGE (HLDA)
Assertion of this output indicates the 80386
has
re-
linquished control of its local bus
in
response to
HOLD
asserted, and
is
in
the bus Hold Acknowledge
state.
The Hold Acknowledge state offers near-complete
signal isolation.
In
the Hold Acknowledge state,
HLDA
is
the only signal being driven by the 80386.
The other output
signals or bidirectional signals
(00-031,
BEO#-BE3#,
A2-A31,
W/R#,
D/C#,
M/IO#,
LOCK# and
ADS#)
are
in
a high-imped-
ance state
so
the requesting bus master
may
control
them.
Pull
up
resistors
may
be
desired
on
several
sig-
nals
to
avoid spurious activity when no bus master
is
driving them. See 7.2.3 Resistor Recommenda-
tions. Also, one rising edge occuring
on
the
NMI
input during Hold Ac!mowledge
is
remembered, for
processing after the HOLD input
is
negated.
64
In
addition to the normal usage of Hold Acknowl-
edge with DMA controllers or master peripherals,
the near-complete isolation
has
particular attractive-
ness during system test when test equipment drives
the system, and
in
hardware-fault-tolerant applica-
tions.
5.2.8 Coprocessor Interface Signals
5.2.8.1 INTRODUCTION
In
the following sections
are
descriptions of signals
dedicated to the numeric coprocessor interface.
In
addition to the data
bus,
address bus, and
bus
cycle
definition signals, these following signals control
communication between the 80386 and its 80287 or
80387 processor extension.
5.2.8.2
COPROCESSOR REQUEST (PEREQ)
When asserted, this input
signal indicates a coproc-
essor request for a data operand to
be
transferred
to/from memory by the 80386.
In
response, the
80386 transfers information between the coproces-
sor and memory. Because the 80386 has internally
stored the coprocessor opcode being executed, it
performs the requested data transfer with the cor-
rect direction and memory address.
PEREQ
is
level-sensitive
and
is
allowed to be asyn-
chronous to the CLK2 signal.
5.2.8.3 COPROCESSOR BUSY (BUSY#)
When asserted, this input indicates the coprocessor
is
still executing
an
instruction, and is not yet able to
accept another. When the 80386 encounters any
coprocessor instruction which operates
on
the nu-
meric stack (e.g. load, pop, or arithmetic operation),
or the
WAIT instruction, this input
is
first automatical-
ly
sampled until it is seen to
be
negated. This sam-
pling of the BUSY# input prevents overrunning the
execution of a previous coprocessor instruction.
The
FNINIT and FNCLEX coprocessor instructions
are
allowed to execute even if
BUSY
# is asserted;
since these instructions are used for coprocessor
initialization and exception-clearing.
BUSY #
is
level-sensitive and
is
allowed to
be
asyn-
chronous to the CLK2 signal.
BUSY # serves
an
additional function. If BUSY #
is
sampled
LOW
at the falling edge of
RESET,
the
80386 performs
an
internal self-test (see 5.5.3 Bus
Activity
During and Following Reset). If BUSY #
is
sampled HIGH,
no
self-test is performed.