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80386
Effect of asserting
B516#
during "upper half only"
read cycles:
Asserting
B516#
during "upper half only" reads
causes the
80386 to read data
on
the lower 16
bits of the data bus and ignore data
on
the upper
16 bits of the data bus. Oata that would have been
read from
016-031
(as indicated
by
BE2# and
BE3
#)
will instead
be
read from
00-015
respec-
tively.
Effect of asserting
B516#
during "upper half only"
write cycles:
Asserting
B516#
during "upper half only" writes
does not affect the
80386. When only BE2 #
and/or BE3# are asserted during a write cycle
the
80386 always duplicates data signals
016-031
onto
00-015
(see Table
5-1).
There-
fore,
no
further 80386 action
is
required to per-
form these writes
on
32-bit or 16-bit buses.
Effect of asserting
B516#
during "upper and lower
half" read cycles:
Asserting
B516#
during "upper and lower half"
reads causes the processor to perform two 16-bit
read cycles for complete physical operand
trans-
fer.
Bytes 0 and 1 (as indicated
by
BEO# and
BE1
#)
are read
on
the first cycle using
00-015.
Bytes 2 and 3
(as
indicated by BE2# and
BE3#)
are
read during the second cycle, again using
00-015.
016-031
are ignored during both 16-bit
cycles.
BEO# and
BE1
# are always negated dur-
ing
the second 16-bit cycle (5ee Figure 5-14, cy-
cles 2 and 2a).
Effect of asserting
B516#
during "upper and lower
half" write cycles:
Asserting
B516#
during "upper and lower half"
writes causes the 80386 to perform two 16-bit
write cycles for complete physical operand
trans-
fer.
All bytes are available the first write cycle al-
lowing external hardware to receive Bytes 0 and 1
(as
indicated
by
BEO# and
BE1
#)
using
00-015.
On
the second cycle the 80386 duplicates Bytes 2
and 3
on
00-015
and Bytes 2 and 3
(as
indicated
by
BE2# and BE3#)
are
written using
00-015.
BEO# and
BE1
# are always negated during the
second 16-bit cycle.
B516#
must
be
asserted
during the second 16-bit cycle.
See Figure 5-14,
cycles 1 and
1a.
5.3.5 Interfacing with 32- and 16-Bit
Memories
In
32-bit-wide physical memories such
as
Figure
5-5,
each physical Oword begins at a byte address that
is
a multiple of
4.
A2-A31 are directly used
as
a
Oword
select and
BEO#-BE3#
as
byte selects.
B516#
is
negated for all bus cycles involving the 32-bit array.
When 16-bit-wide physical arrays are included
in
the
system, as
in
Figure
5-6,
each 16-bit physical word
begins at a address that
is
a multiple of
2.
Note the
address
is
decoded, to assert
B516#
only during
bus cycles involving the 16-bit array.
(If desiring to use
32
DATA
BUS
(00-031)
80386
ADDRESS
BUS
(BEO#-BE3#,A2-A31)
i
BS16
#
"HIGH"
32-BIT
MEMORY
Figure 5-5. 80386 with 32-Bit Memory
DATA
BUS
(00-031)
ADDRESS
BUS
(BEO#-BE3#,
A2-A31)
16
DATA
BUS
(00-015)
Figure 5-6. 80386 with 32-Bit and 16-Bit Memory
69
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