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HARDWARE IMPLEMENTATION
Pipelining instruction fetch, decode, and execu-
tion units on a single chip
is
not unusual in
modern microprocessors.
On the other hand,
placing the memory management unit
(MMU)
in the on-chip pipeline
is
quite unusual. Incor-
porating the
MMU
on the processor chip im-
proves the speed
of
addresss translation by
reducing signal propagation delays (most off-
chip
MMUs introduce
at
least one wait state),
and exploiting the half-clock boundaries that are
accessible within the chip (the
80386 clock input
is
twice the frequency
of
the chip). The 80386
80287
OR
80387
NUMERIC
COPROCESSOR
82384
CLOCK
GENERATOR
80386
CPU
INTR
MMU
consists
of
the segment and page units
shown in Figure 5-1.
The
segment unit translates logical addresses to
linear addresses, and checks each access for
consistency with segment protection attributes.
For
the majority
of
instructions, the segment
unit obtains the translation and protection data
from the 80386's on-chip segment and descriptor
registers. The
page unit
is
enabled
or
disabled by
operating system software. When disabled, the
linear addresses produced
by
the segment unit
OPTIONAL
CACHE
CONTROL
DRAM
CONTROL
MULTIBUS
1/11
INTERFACE
82258
ADVANCED
DMA
DRAM
K:====:>
MULTIBUS®
1/11
LOCAL
BUS
CONTROL
EPROM
Figure 5-2. Representative System Block Diagram
5-2