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80386
5.2.10
Signal Summary
Table
5-4
summarizes the characteristics of all 80386 signals.
Table
5-4_
80386 Signal Summary
Signal Name Signal Function
CLK2
Clock
00-031
Data
Bus
BEO#-BE3#
Byte Enables
A2-A31
Address
Bus
W/R#
Write-Read Indication
OfC#
Data-Control Indication
M/IO#
Memory-I/O Indication
LOCK#
Bus
Lock Indication
ADS#
Address Status
NA#
Next Address Request
BS16#
Bus
Size 16
REAOY#
Transfer Acknowledge
HOLD
Bus
Hold Request
HLOA
Bus
Hold Acknowledge
PEREO
Coprocessor Request
BUSY#
Coprocessor Busy
ERROR# Coprocessor Error
INTR
Maskable Interrupt Request
NMI
Non-Maskable Intrpt Request
RESET
Reset
5.3 BUS TRANSFER MECHANISM
5.3.1
Introduction
All data transfers occur
as
a result of one or more
bus
cycles. Logical data operands of byte, word and
double-word lengths
may
be
transferred without
re-
strictions
on
physical address alignment. Any byte
boundary may
be
used, although two or even three
physical bus cycles are performed
as
required for
unaligned operand transfers. See
5_3.4
Dynamic
Data Bus Sizing and 5,3.6
Operand Alignment.
Input
Output
Active
Input!
Synch
or
High Impedance
State
Output
Asynch
During HLDA?
toCLK2
- I -
-
High
1/0
S Yes
Low 0
-
Yes
High 0
-
Yes
High 0 - Yes
High 0
-
Yes
High 0
-
Yes
Low 0
-
Yes
Low a -
Yes
Low I S -
Low I S
-
Low I S
-
High I S -
High a -
No
High I A
-
Low I A -
Low I A
-
High I A
-
High I A
-
High
I S
-
The 80386 address signals are designed to simplify
external
system hardware. Higher-order address bits
are provided
by
A2-A31.
Lower-order address
in
the
form of
BEO#
-BE3#
directly provides linear selects
for the four bytes of the 32-bit data
bus.
Physical
operand size information is thereby implicitly provid-
ed
each
bus
cycle
in
the most usable form.
66
Byte Enable outputs
BEO#-BE3#
are
asserted
when their associated data bus bytes are
involved
with the present bus cycle,
as
listed
in
Table
5-5.
During a bus cycle, any possible pattern of contigu-
ous,
asserted Byte Enable outputs can occur, but
never patterns having a negated Byte
Enable sepa-
rating two or three asserted Enables.